2017-01-18 12:05:26 +00:00
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menu "ESP32-specific"
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2016-08-17 15:08:22 +00:00
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2016-09-13 10:10:58 +00:00
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choice ESP32_DEFAULT_CPU_FREQ_MHZ
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prompt "CPU frequency"
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default ESP32_DEFAULT_CPU_FREQ_240
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help
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CPU frequency to be set on application startup.
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config ESP32_DEFAULT_CPU_FREQ_80
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bool "80 MHz"
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config ESP32_DEFAULT_CPU_FREQ_160
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bool "160 MHz"
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config ESP32_DEFAULT_CPU_FREQ_240
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bool "240 MHz"
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endchoice
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config ESP32_DEFAULT_CPU_FREQ_MHZ
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int
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default 80 if ESP32_DEFAULT_CPU_FREQ_80
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default 160 if ESP32_DEFAULT_CPU_FREQ_160
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default 240 if ESP32_DEFAULT_CPU_FREQ_240
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2016-09-22 10:36:23 +00:00
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config MEMMAP_SMP
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bool "Reserve memory for two cores"
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default "y"
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help
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The ESP32 contains two cores. If you plan to only use one, you can disable this item
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to save some memory. (ToDo: Make this automatically depend on unicore support)
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config MEMMAP_TRACEMEM
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bool "Use TRAX tracing feature"
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default "n"
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help
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The ESP32 contains a feature which allows you to trace the execution path the processor
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has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
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of memory that can't be used for general purposes anymore. Disable this if you do not know
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what this is.
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2016-10-17 04:18:17 +00:00
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config MEMMAP_TRACEMEM_TWOBANKS
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bool "Reserve memory for tracing both pro as well as app cpu execution"
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default "n"
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depends on MEMMAP_TRACEMEM && MEMMAP_SMP
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help
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The ESP32 contains a feature which allows you to trace the execution path the processor
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has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
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of memory that can't be used for general purposes anymore. Disable this if you do not know
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what this is.
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2016-09-28 04:27:25 +00:00
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# Memory to reverse for trace, used in linker script
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config TRACEMEM_RESERVE_DRAM
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hex
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2016-10-17 04:18:17 +00:00
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default 0x8000 if MEMMAP_TRACEMEM && MEMMAP_TRACEMEM_TWOBANKS
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default 0x4000 if MEMMAP_TRACEMEM && !MEMMAP_TRACEMEM_TWOBANKS
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2016-09-28 04:27:25 +00:00
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default 0x0
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2016-12-21 23:56:23 +00:00
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choice ESP32_COREDUMP_TO_FLASH_OR_UART
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prompt "Core dump destination"
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default ESP32_ENABLE_COREDUMP_TO_NONE
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help
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Select place to store core dump: flash, uart or none (to disable core dumps generation).
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If core dump is configured to be stored in flash and custom partition table is used add
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corresponding entry to your CSV. For examples, please see predefined partition table CSV descriptions
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in the components/partition_table directory.
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config ESP32_ENABLE_COREDUMP_TO_FLASH
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bool "Flash"
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2017-01-10 11:48:47 +00:00
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select ESP32_ENABLE_COREDUMP
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2016-12-21 23:56:23 +00:00
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config ESP32_ENABLE_COREDUMP_TO_UART
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bool "UART"
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2017-01-10 11:48:47 +00:00
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select ESP32_ENABLE_COREDUMP
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2016-12-21 23:56:23 +00:00
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config ESP32_ENABLE_COREDUMP_TO_NONE
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bool "None"
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endchoice
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2017-01-10 11:48:47 +00:00
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config ESP32_ENABLE_COREDUMP
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bool
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default F
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help
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Enables/disable core dump module.
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config ESP32_CORE_DUMP_UART_DELAY
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int "Core dump print to UART delay"
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depends on ESP32_ENABLE_COREDUMP_TO_UART
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default 0
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help
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Config delay (in ms) before printing core dump to UART.
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Delay can be interrupted by pressing Enter key.
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config ESP32_CORE_DUMP_LOG_LEVEL
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int "Core dump module logging level"
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depends on ESP32_ENABLE_COREDUMP
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default 1
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help
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Config core dump module logging level (0-5).
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2017-02-20 07:18:58 +00:00
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config MEMMAP_SPIRAM_ENABLE
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2017-02-20 11:33:17 +00:00
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bool "Capability allocator can allocate SPI RAM memory"
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2016-09-22 10:36:23 +00:00
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default "n"
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help
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2017-02-20 07:18:58 +00:00
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The ESP32 can control an external SPI RAM chip, adding the memory it contains to the
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2017-02-20 11:33:17 +00:00
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memory map. Enable this if you have this hardware (eg when you have the ESP-WROVER module, or
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a board containing that module) and want to allocate memory from it using
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pvPortMallocCaps(size, MALLOC_CAP_SPIRAM ); This also enables the code that initializes the
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RAM chip.
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2017-02-20 07:18:58 +00:00
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This only works correctly with v1 (post Feb 2017) silicon.
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2017-02-21 06:00:05 +00:00
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if MEMMAP_SPIRAM_ENABLE
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2017-03-21 03:42:53 +00:00
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config SPIRAM_CACHE_WORKAROUND
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bool "Enable workaround for bug in SPI RAM cache for V1 silicon"
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default "y"
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help
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V1 ESP32 silicon has a bug that can cause a write to PSRAM not to take place in some situations
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when the cache line needs to be fetched from external RAM and an interrupt occurs. This enables a
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fix in the compiler that makes sure the specific code that is vulnerable to this will not be emitted.
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2017-03-27 07:01:30 +00:00
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config SPIRAM_CACHE_ALWAYS_MEMBARRIER
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bool "Heavy-handed workaround for bug: Always do memory barrier"
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default "n"
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help
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This will introduce a memory barrier before EVERY load/store. This will get rid of most coherency
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issues, but at the cost of a lot of performance. Don't enable unless you know you need this!
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2017-03-21 09:01:25 +00:00
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config SPIRAM_CACHE_WORKAROUND_TEST
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bool "Debug: Test workaround by generating a lot of interrupts"
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default "n"
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help
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This setting helps testing the SPIRAM cache workaround. It generates a lot of interrupts so
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the bug, if still existing, triggers quicker.
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2017-02-20 07:18:58 +00:00
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choice MEMMAP_SPIRAM_TYPE
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prompt "Type of SPI RAM chip in use"
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default MEMMAP_SPIRAM_TYPE_ESPPSRAM32
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config MEMMAP_SPIRAM_TYPE_ESPPSRAM32
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bool "ESP-PSRAM32 or IS25WP032"
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endchoice
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2017-02-21 06:00:05 +00:00
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config MEMMAP_SPIRAM_SIZE
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int
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default 4194304 if MEMMAP_SPIRAM_ENABLE && MEMMAP_SPIRAM_TYPE_ESPPSRAM32
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default 0
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help
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Size of external SPI RAM
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2017-03-07 10:38:27 +00:00
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config MEMMAP_SPIRAM_NO_HEAPALLOC
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bool "Initialize PSRAM memory but do not add to heap allocator"
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default "n"
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help
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This initializes the PSRAM as normal, but does not make the heap allocator aware of the
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memory region. You can use the memory region from 0x3F800000-0x3FBFFFFF freely, but
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need to do your own memory management there.
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2017-02-20 11:33:17 +00:00
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config MEMMAP_SPIRAM_TEST
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bool "On SPI RAM init, do a quick memory test"
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2017-03-07 10:38:27 +00:00
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depends on !MEMMAP_SPIRAM_NO_HEAPALLOC
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2017-02-20 11:33:17 +00:00
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default "n"
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help
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This does a quick memory test on boot-up. This takes about a second for 4MiB of SPI RAM.
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2017-02-20 07:18:58 +00:00
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2017-02-20 11:33:17 +00:00
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config MEMMAP_SPIRAM_ENABLE_MALLOC
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bool "malloc() can also allocate in SPI SRAM"
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2017-03-08 12:42:57 +00:00
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depends on !MEMMAP_SPIRAM_NO_HEAPALLOC
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2017-02-20 11:33:17 +00:00
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default "n"
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help
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If enabled, malloc() will return pointers to both internal as well as external
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RAM. It will use a heuristic to determine when to return which. For now, the
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heuristic is to allocate internal RAM for anything smaller than
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MEMMAP_SPIRAM_ALLOC_LIMIT_INTERNAL bytes and external RAM for bigger sizes.
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config MEMMAP_SPIRAM_ALLOC_LIMIT_INTERNAL
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int "Always put malloc()s smaller than this size, in bytes, in internal RAM"
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depends on MEMMAP_SPIRAM_ENABLE_MALLOC
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2017-03-07 10:38:27 +00:00
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range 4096 4194304
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default 4096
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help
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Always tries to allocate heap allocation requests smaller than defined here in
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internal RAM instead of PSRAM; allocations larger than this will initially
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go to PSRAM. If either of these initial allocations fails, allocation in the
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other memory region will be attempted as a backup option.
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2016-09-22 10:36:23 +00:00
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2017-02-21 06:00:05 +00:00
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endif
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2017-03-02 06:57:45 +00:00
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choice NUMBER_OF_MAC_ADDRESS_GENERATED_FROM_EFUSE
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bool "Number of MAC address generated from the hardware MAC address in efuse"
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default FOUR_MAC_ADDRESS_FROM_EFUSE
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help
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Config the number of MAC address which is generated from the hardware MAC address in efuse.
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If the number is two, the MAC addresses of WiFi station and bluetooth are generated from
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the hardware MAC address in efuse. The MAC addresses of WiFi softap and ethernet are derived
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from that of WiFi station and bluetooth respectively.
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If the number is four, the MAC addresses of WiFi station, WiFi softap, bluetooth and ethernet
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are all generated from the hardware MAC address in efuse.
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config TWO_MAC_ADDRESS_FROM_EFUSE
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bool "Two"
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config FOUR_MAC_ADDRESS_FROM_EFUSE
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bool "Four"
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endchoice
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config NUMBER_OF_MAC_ADDRESS_GENERATED_FROM_EFUSE
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int
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default 2 if TWO_MAC_ADDRESS_FROM_EFUSE
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default 4 if FOUR_MAC_ADDRESS_FROM_EFUSE
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2016-09-14 05:26:17 +00:00
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config SYSTEM_EVENT_QUEUE_SIZE
|
2016-09-25 16:50:57 +00:00
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int "System event queue size"
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2016-08-17 15:08:22 +00:00
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default 32
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help
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2016-09-14 04:55:41 +00:00
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Config system event queue size in different application.
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2016-08-17 15:08:22 +00:00
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2016-09-14 04:55:41 +00:00
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config SYSTEM_EVENT_TASK_STACK_SIZE
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2016-09-25 16:50:57 +00:00
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int "Event loop task stack size"
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2017-01-16 09:06:12 +00:00
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default 4096
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2016-09-25 16:50:57 +00:00
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help
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Config system event task stack size in different application.
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config MAIN_TASK_STACK_SIZE
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int "Main task stack size"
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default 4096
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2016-08-17 15:08:22 +00:00
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help
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2016-09-14 04:55:41 +00:00
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Config system event task stack size in different application.
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2016-08-17 15:08:22 +00:00
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2016-08-23 07:02:27 +00:00
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config NEWLIB_STDOUT_ADDCR
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2016-09-28 05:24:58 +00:00
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bool "Standard-out output adds carriage return before newline"
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default y
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help
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Most people are used to end their printf strings with a newline. If this
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is sent as is to the serial port, most terminal programs will only move the
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cursor one line down, not also move it to the beginning of the line. This
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is usually done by an added CR character. Enabling this will make the
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standard output code automatically add a CR character before a LF.
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2017-01-09 14:50:42 +00:00
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With this option enabled, C standard library functions which read from UART
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(like scanf) will convert "\r\n" character sequences back to "\n".
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This option doesn't affect behavior of the UART driver (drivers/uart.h).
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2016-08-23 07:02:27 +00:00
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2016-11-07 10:43:29 +00:00
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config NEWLIB_NANO_FORMAT
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bool "Enable 'nano' formatting options for printf/scanf family"
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default n
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help
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ESP32 ROM contains parts of newlib C library, including printf/scanf family
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of functions. These functions have been compiled with so-called "nano"
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formatting option. This option doesn't support 64-bit integer formats and C99
|
2017-01-10 05:04:04 +00:00
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features, such as positional arguments.
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2016-11-07 10:43:29 +00:00
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For more details about "nano" formatting option, please see newlib readme file,
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search for '--enable-newlib-nano-formatted-io':
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https://sourceware.org/newlib/README
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If this option is enabled, build system will use functions available in
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ROM, reducing the application binary size. Functions available in ROM run
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faster than functions which run from flash. Functions available in ROM can
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also run when flash instruction cache is disabled.
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If you need 64-bit integer formatting support or C99 features, keep this
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option disabled.
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|
2016-10-27 08:17:28 +00:00
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choice CONSOLE_UART
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prompt "UART for console output"
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default CONSOLE_UART_DEFAULT
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help
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Select whether to use UART for console output (through stdout and stderr).
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- Default is to use UART0 on pins GPIO1(TX) and GPIO3(RX).
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- If "Custom" is selected, UART0 or UART1 can be chosen,
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and any pins can be selected.
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- If "None" is selected, there will be no console output on any UART, except
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for initial output from ROM bootloader. This output can be further suppressed by
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bootstrapping GPIO13 pin to low logic level.
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config CONSOLE_UART_DEFAULT
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bool "Default: UART0, TX=GPIO1, RX=GPIO3"
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config CONSOLE_UART_CUSTOM
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bool "Custom"
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config CONSOLE_UART_NONE
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bool "None"
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endchoice
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choice CONSOLE_UART_NUM
|
2017-01-10 05:04:04 +00:00
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prompt "UART peripheral to use for console output (0-1)"
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depends on CONSOLE_UART_CUSTOM
|
2016-10-27 08:17:28 +00:00
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default CONSOLE_UART_CUSTOM_NUM_0
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help
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2017-01-10 05:04:04 +00:00
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Due of a ROM bug, UART2 is not supported for console output
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via ets_printf.
|
2016-10-27 08:17:28 +00:00
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config CONSOLE_UART_CUSTOM_NUM_0
|
2017-01-10 05:04:04 +00:00
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bool "UART0"
|
2016-10-27 08:17:28 +00:00
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config CONSOLE_UART_CUSTOM_NUM_1
|
2017-01-10 05:04:04 +00:00
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bool "UART1"
|
2016-10-27 08:17:28 +00:00
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endchoice
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config CONSOLE_UART_NUM
|
2017-01-10 05:04:04 +00:00
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int
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default 0 if CONSOLE_UART_DEFAULT || CONSOLE_UART_NONE
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default 0 if CONSOLE_UART_CUSTOM_NUM_0
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default 1 if CONSOLE_UART_CUSTOM_NUM_1
|
2016-10-27 08:17:28 +00:00
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config CONSOLE_UART_TX_GPIO
|
2017-01-10 05:04:04 +00:00
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int "UART TX on GPIO#"
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depends on CONSOLE_UART_CUSTOM
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range 0 33
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default 19
|
2016-10-27 08:17:28 +00:00
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config CONSOLE_UART_RX_GPIO
|
2017-01-10 05:04:04 +00:00
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int "UART RX on GPIO#"
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depends on CONSOLE_UART_CUSTOM
|
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range 0 39
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default 21
|
2016-10-27 08:17:28 +00:00
|
|
|
|
|
|
|
config CONSOLE_UART_BAUDRATE
|
2017-01-10 05:04:04 +00:00
|
|
|
int "UART console baud rate"
|
|
|
|
depends on !CONSOLE_UART_NONE
|
|
|
|
default 115200
|
|
|
|
range 1200 4000000
|
2016-10-27 08:17:28 +00:00
|
|
|
|
2016-09-21 01:24:02 +00:00
|
|
|
config ULP_COPROC_ENABLED
|
|
|
|
bool "Enable Ultra Low Power (ULP) Coprocessor"
|
|
|
|
default "n"
|
|
|
|
help
|
2016-09-28 05:24:58 +00:00
|
|
|
Set to 'y' if you plan to load a firmware for the coprocessor.
|
2016-09-21 01:24:02 +00:00
|
|
|
|
2016-09-28 05:24:58 +00:00
|
|
|
If this option is enabled, further coprocessor configuration will appear in the Components menu.
|
2016-09-21 01:24:02 +00:00
|
|
|
|
|
|
|
config ULP_COPROC_RESERVE_MEM
|
2016-09-28 05:24:58 +00:00
|
|
|
int "RTC slow memory reserved for coprocessor"
|
|
|
|
default 512
|
|
|
|
range 32 8192
|
|
|
|
depends on ULP_COPROC_ENABLED
|
|
|
|
help
|
|
|
|
Bytes of memory to reserve for ULP coprocessor firmware & data.
|
2016-09-21 01:24:02 +00:00
|
|
|
|
2016-09-28 05:24:58 +00:00
|
|
|
Data is reserved at the beginning of RTC slow memory.
|
2016-09-21 01:24:02 +00:00
|
|
|
|
|
|
|
# Set CONFIG_ULP_COPROC_RESERVE_MEM to 0 if ULP is disabled
|
|
|
|
config ULP_COPROC_RESERVE_MEM
|
2016-09-28 05:24:58 +00:00
|
|
|
int
|
|
|
|
default 0
|
|
|
|
depends on !ULP_COPROC_ENABLED
|
2016-09-21 01:24:02 +00:00
|
|
|
|
2016-10-21 09:59:57 +00:00
|
|
|
|
2016-10-26 04:23:01 +00:00
|
|
|
choice ESP32_PANIC
|
|
|
|
prompt "Panic handler behaviour"
|
2016-10-28 04:05:42 +00:00
|
|
|
default ESP32_PANIC_PRINT_REBOOT
|
2016-10-26 04:23:01 +00:00
|
|
|
help
|
2017-01-10 05:04:04 +00:00
|
|
|
If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is
|
2016-10-26 04:23:01 +00:00
|
|
|
invoked. Configure the panic handlers action here.
|
|
|
|
|
|
|
|
config ESP32_PANIC_PRINT_HALT
|
|
|
|
bool "Print registers and halt"
|
|
|
|
help
|
2017-01-10 05:04:04 +00:00
|
|
|
Outputs the relevant registers over the serial port and halt the
|
2016-10-26 04:23:01 +00:00
|
|
|
processor. Needs a manual reset to restart.
|
|
|
|
|
|
|
|
config ESP32_PANIC_PRINT_REBOOT
|
|
|
|
bool "Print registers and reboot"
|
|
|
|
help
|
|
|
|
Outputs the relevant registers over the serial port and immediately
|
|
|
|
reset the processor.
|
|
|
|
|
|
|
|
config ESP32_PANIC_SILENT_REBOOT
|
|
|
|
bool "Silent reboot"
|
|
|
|
help
|
|
|
|
Just resets the processor without outputting anything
|
|
|
|
|
|
|
|
config ESP32_PANIC_GDBSTUB
|
|
|
|
bool "Invoke GDBStub"
|
|
|
|
help
|
|
|
|
Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem
|
|
|
|
of the crash.
|
|
|
|
endchoice
|
|
|
|
|
|
|
|
config ESP32_DEBUG_OCDAWARE
|
|
|
|
bool "Make exception and panic handlers JTAG/OCD aware"
|
|
|
|
default y
|
|
|
|
help
|
|
|
|
The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and
|
|
|
|
instead of panicking, have the debugger stop on the offending instruction.
|
|
|
|
|
|
|
|
|
2016-10-21 09:59:57 +00:00
|
|
|
config INT_WDT
|
|
|
|
bool "Interrupt watchdog"
|
|
|
|
default y
|
|
|
|
help
|
|
|
|
This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,
|
|
|
|
either because a task turned off interrupts and did not turn them on for a long time, or because an
|
|
|
|
interrupt handler did not return. It will try to invoke the panic handler first and failing that
|
|
|
|
reset the SoC.
|
|
|
|
|
|
|
|
config INT_WDT_TIMEOUT_MS
|
|
|
|
int "Interrupt watchdog timeout (ms)"
|
|
|
|
depends on INT_WDT
|
2016-10-28 08:17:41 +00:00
|
|
|
default 300
|
2016-10-25 09:05:13 +00:00
|
|
|
range 10 10000
|
2016-10-21 09:59:57 +00:00
|
|
|
help
|
2016-10-21 11:30:29 +00:00
|
|
|
The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
|
2016-10-21 09:59:57 +00:00
|
|
|
|
2016-10-25 10:08:55 +00:00
|
|
|
config INT_WDT_CHECK_CPU1
|
|
|
|
bool "Also watch CPU1 tick interrupt"
|
|
|
|
depends on INT_WDT && !FREERTOS_UNICORE
|
|
|
|
default y
|
|
|
|
help
|
|
|
|
Also detect if interrupts on CPU 1 are disabled for too long.
|
|
|
|
|
2016-10-21 09:59:57 +00:00
|
|
|
config TASK_WDT
|
|
|
|
bool "Task watchdog"
|
|
|
|
default y
|
|
|
|
help
|
|
|
|
This watchdog timer can be used to make sure individual tasks are still running.
|
|
|
|
|
|
|
|
config TASK_WDT_PANIC
|
|
|
|
bool "Invoke panic handler when Task Watchdog is triggered"
|
|
|
|
depends on TASK_WDT
|
|
|
|
default n
|
|
|
|
help
|
|
|
|
Normally, the Task Watchdog will only print out a warning if it detects it has not
|
|
|
|
been fed. If this is enabled, it will invoke the panic handler instead, which
|
|
|
|
can then halt or reboot the chip.
|
|
|
|
|
|
|
|
config TASK_WDT_TIMEOUT_S
|
|
|
|
int "Task watchdog timeout (seconds)"
|
|
|
|
depends on TASK_WDT
|
|
|
|
range 1 60
|
|
|
|
default 5
|
|
|
|
help
|
|
|
|
Timeout for the task WDT, in seconds.
|
|
|
|
|
|
|
|
config TASK_WDT_CHECK_IDLE_TASK
|
2016-10-25 10:08:55 +00:00
|
|
|
bool "Task watchdog watches CPU0 idle task"
|
2016-10-21 09:59:57 +00:00
|
|
|
depends on TASK_WDT
|
|
|
|
default y
|
|
|
|
help
|
|
|
|
With this turned on, the task WDT can detect if the idle task is not called within the task
|
|
|
|
watchdog timeout period. The idle task not being called usually is a symptom of another
|
2017-01-10 05:04:04 +00:00
|
|
|
task hoarding the CPU. It is also a bad thing because FreeRTOS household tasks depend on the
|
|
|
|
idle task getting some runtime every now and then. Take Care: With this disabled, this
|
2016-10-25 09:05:13 +00:00
|
|
|
watchdog will trigger if no tasks register themselves within the timeout value.
|
2016-10-21 09:59:57 +00:00
|
|
|
|
2016-10-25 10:08:55 +00:00
|
|
|
config TASK_WDT_CHECK_IDLE_TASK_CPU1
|
|
|
|
bool "Task watchdog also watches CPU1 idle task"
|
|
|
|
depends on TASK_WDT_CHECK_IDLE_TASK && !FREERTOS_UNICORE
|
|
|
|
default y
|
|
|
|
help
|
|
|
|
Also check the idle task that runs on CPU1.
|
|
|
|
|
2016-10-25 09:05:13 +00:00
|
|
|
#The brownout detector code is disabled (by making it depend on a nonexisting symbol) because the current revision of ESP32
|
|
|
|
#silicon has a bug in the brown-out detector, rendering it unusable for resetting the CPU.
|
2016-10-21 09:59:57 +00:00
|
|
|
config BROWNOUT_DET
|
|
|
|
bool "Hardware brownout detect & reset"
|
|
|
|
default y
|
2016-10-25 09:05:13 +00:00
|
|
|
depends on NEEDS_ESP32_NEW_SILICON_REV
|
2016-10-21 09:59:57 +00:00
|
|
|
help
|
2017-01-10 05:04:04 +00:00
|
|
|
The ESP32 has a built-in brownout detector which can detect if the voltage is lower than
|
2016-10-21 09:59:57 +00:00
|
|
|
a specific value. If this happens, it will reset the chip in order to prevent unintended
|
|
|
|
behaviour.
|
|
|
|
|
|
|
|
choice BROWNOUT_DET_LVL_SEL
|
|
|
|
prompt "Brownout voltage level"
|
|
|
|
depends on BROWNOUT_DET
|
|
|
|
default BROWNOUT_DET_LVL_SEL_25
|
|
|
|
help
|
|
|
|
The brownout detector will reset the chip when the supply voltage is below this level.
|
|
|
|
|
2016-10-25 09:05:13 +00:00
|
|
|
#The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
|
|
|
|
#of the brownout threshold levels.
|
2016-10-21 09:59:57 +00:00
|
|
|
config BROWNOUT_DET_LVL_SEL_0
|
|
|
|
bool "2.1V"
|
|
|
|
config BROWNOUT_DET_LVL_SEL_1
|
|
|
|
bool "2.2V"
|
|
|
|
config BROWNOUT_DET_LVL_SEL_2
|
|
|
|
bool "2.3V"
|
|
|
|
config BROWNOUT_DET_LVL_SEL_3
|
|
|
|
bool "2.4V"
|
|
|
|
config BROWNOUT_DET_LVL_SEL_4
|
|
|
|
bool "2.5V"
|
|
|
|
config BROWNOUT_DET_LVL_SEL_5
|
|
|
|
bool "2.6V"
|
|
|
|
config BROWNOUT_DET_LVL_SEL_6
|
|
|
|
bool "2.7V"
|
|
|
|
config BROWNOUT_DET_LVL_SEL_7
|
|
|
|
bool "2.8V"
|
|
|
|
endchoice
|
|
|
|
|
|
|
|
config BROWNOUT_DET_LVL
|
|
|
|
int
|
|
|
|
default 0 if BROWNOUT_DET_LVL_SEL_0
|
|
|
|
default 1 if BROWNOUT_DET_LVL_SEL_1
|
|
|
|
default 2 if BROWNOUT_DET_LVL_SEL_2
|
|
|
|
default 3 if BROWNOUT_DET_LVL_SEL_3
|
|
|
|
default 4 if BROWNOUT_DET_LVL_SEL_4
|
|
|
|
default 5 if BROWNOUT_DET_LVL_SEL_5
|
|
|
|
default 6 if BROWNOUT_DET_LVL_SEL_6
|
|
|
|
default 7 if BROWNOUT_DET_LVL_SEL_7
|
|
|
|
|
|
|
|
|
|
|
|
config BROWNOUT_DET_RESETDELAY
|
|
|
|
int "Brownout reset delay (in uS)"
|
|
|
|
depends on BROWNOUT_DET
|
|
|
|
range 0 6820
|
|
|
|
default 1000
|
|
|
|
help
|
|
|
|
The brownout detector can reset the chip after a certain delay, in order to make sure e.g. a voltage dip has entirely passed
|
|
|
|
before trying to restart the chip. You can set the delay here.
|
|
|
|
|
|
|
|
|
2016-11-02 09:17:28 +00:00
|
|
|
choice ESP32_TIME_SYSCALL
|
2017-01-10 05:04:04 +00:00
|
|
|
prompt "Timers used for gettimeofday function"
|
|
|
|
default ESP32_TIME_SYSCALL_USE_RTC_FRC1
|
|
|
|
help
|
|
|
|
This setting defines which hardware timers are used to
|
|
|
|
implement 'gettimeofday' and 'time' functions in C library.
|
|
|
|
|
|
|
|
- If only FRC1 timer is used, gettimeofday will provide time at
|
|
|
|
microsecond resolution. Time will not be preserved when going
|
|
|
|
into deep sleep mode.
|
|
|
|
- If both FRC1 and RTC timers are used, timekeeping will
|
|
|
|
continue in deep sleep. Time will be reported at 1 microsecond
|
|
|
|
resolution.
|
|
|
|
- If only RTC timer is used, timekeeping will continue in
|
|
|
|
deep sleep, but time will be measured at 6.(6) microsecond
|
|
|
|
resolution. Also the gettimeofday function itself may take
|
|
|
|
longer to run.
|
|
|
|
- If no timers are used, gettimeofday and time functions
|
|
|
|
return -1 and set errno to ENOSYS.
|
2017-01-11 09:28:09 +00:00
|
|
|
- When RTC is used for timekeeping, two RTC_STORE registers are
|
|
|
|
used to keep time in deep sleep mode.
|
2017-01-10 05:04:04 +00:00
|
|
|
|
2016-11-02 09:17:28 +00:00
|
|
|
config ESP32_TIME_SYSCALL_USE_RTC
|
|
|
|
bool "RTC"
|
|
|
|
config ESP32_TIME_SYSCALL_USE_RTC_FRC1
|
|
|
|
bool "RTC and FRC1"
|
|
|
|
config ESP32_TIME_SYSCALL_USE_FRC1
|
|
|
|
bool "FRC1"
|
|
|
|
config ESP32_TIME_SYSCALL_USE_NONE
|
|
|
|
bool "None"
|
|
|
|
endchoice
|
2016-10-21 09:59:57 +00:00
|
|
|
|
2016-11-03 06:49:05 +00:00
|
|
|
choice ESP32_RTC_CLOCK_SOURCE
|
2017-01-10 05:04:04 +00:00
|
|
|
prompt "RTC clock source"
|
|
|
|
default ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
|
|
|
|
help
|
|
|
|
Choose which clock is used as RTC clock source.
|
|
|
|
The only available option for now is to use internal
|
|
|
|
150kHz RC oscillator.
|
2016-11-03 06:49:05 +00:00
|
|
|
|
|
|
|
config ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
|
2017-01-10 05:04:04 +00:00
|
|
|
bool "Internal RC"
|
2016-11-03 06:49:05 +00:00
|
|
|
config ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
|
2017-01-10 05:04:04 +00:00
|
|
|
bool "External 32kHz crystal"
|
|
|
|
depends on DOCUMENTATION_FOR_RTC_CNTL
|
2016-11-03 06:49:05 +00:00
|
|
|
endchoice
|
2016-10-21 09:59:57 +00:00
|
|
|
|
2016-12-12 15:20:15 +00:00
|
|
|
config ESP32_DEEP_SLEEP_WAKEUP_DELAY
|
2017-01-10 05:04:04 +00:00
|
|
|
int "Extra delay in deep sleep wake stub (in us)"
|
|
|
|
default 0
|
|
|
|
range 0 5000
|
|
|
|
help
|
|
|
|
When ESP32 exits deep sleep, the CPU and the flash chip are powered on
|
|
|
|
at the same time. CPU will run deep sleep stub first, and then
|
|
|
|
proceed to load code from flash. Some flash chips need sufficient
|
|
|
|
time to pass between power on and first read operation. By default,
|
|
|
|
without any extra delay, this time is approximately 900us.
|
|
|
|
|
|
|
|
If you are using a flash chip which needs more than 900us to become
|
|
|
|
ready after power on, set this parameter to add extra delay
|
|
|
|
to the default deep sleep stub.
|
2016-12-12 15:20:15 +00:00
|
|
|
|
2017-01-10 05:04:04 +00:00
|
|
|
If you are seeing "flash read err, 1000" message printed to the
|
|
|
|
console after deep sleep reset, try increasing this value.
|
|
|
|
|
|
|
|
endmenu
|
|
|
|
|
2017-01-10 05:39:43 +00:00
|
|
|
menuconfig WIFI_ENABLED
|
|
|
|
bool "WiFi"
|
2017-01-10 05:04:04 +00:00
|
|
|
default y
|
2017-01-10 05:39:43 +00:00
|
|
|
help
|
|
|
|
Select this option to enable WiFi stack and show the submenu with WiFi configuration choices.
|
2017-01-10 05:04:04 +00:00
|
|
|
|
|
|
|
config SW_COEXIST_ENABLE
|
|
|
|
bool "Software controls WiFi/Bluetooth coexistence"
|
|
|
|
depends on WIFI_ENABLED && BT_ENABLED
|
|
|
|
default n
|
|
|
|
help
|
|
|
|
If enabled, WiFi & Bluetooth coexistence is controlled by software rather than hardware.
|
|
|
|
Recommended for heavy traffic scenarios. Both coexistence configuration options are
|
|
|
|
automatically managed, no user intervention is required.
|
2016-12-12 15:20:15 +00:00
|
|
|
|
2017-01-18 12:05:26 +00:00
|
|
|
|
2017-02-21 06:52:25 +00:00
|
|
|
config ESP32_WIFI_STATIC_RX_BUFFER_NUM
|
|
|
|
int "Max number of WiFi static RX buffers"
|
2017-01-18 12:05:26 +00:00
|
|
|
depends on WIFI_ENABLED
|
|
|
|
range 2 25
|
2017-02-10 02:28:03 +00:00
|
|
|
default 10
|
2017-01-18 12:05:26 +00:00
|
|
|
help
|
2017-02-21 06:52:25 +00:00
|
|
|
Set the number of WiFi static rx buffers. Each buffer takes approximately 1.6KB of RAM.
|
|
|
|
The static rx buffers are allocated when esp_wifi_init is called, they are not freed
|
|
|
|
until esp_wifi_deinit is called.
|
|
|
|
WiFi hardware use these buffers to receive packets, generally larger number for higher
|
|
|
|
throughput but more memory, smaller number for lower throughput but less memory.
|
|
|
|
|
|
|
|
config ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM
|
|
|
|
int "Max number of WiFi dynamic RX buffers"
|
|
|
|
depends on WIFI_ENABLED
|
|
|
|
range 0 64
|
|
|
|
default 0
|
|
|
|
help
|
|
|
|
Set the number of WiFi dynamic rx buffers, 0 means no limitation for dynamic rx buffer
|
|
|
|
allocation. The size of dynamic rx buffers is not fixed.
|
|
|
|
For each received packet in static rx buffers, WiFi driver makes a copy
|
|
|
|
to dynamic rx buffers and then deliver it to high layer stack. The dynamic rx buffer
|
|
|
|
is freed when the application, such as socket, successfully received the packet.
|
|
|
|
For some applications, the WiFi driver receiving speed is faster than application
|
|
|
|
consuming speed, we may run out of memory if no limitation for the dynamic rx buffer
|
|
|
|
number. Generally the number of dynamic rx buffer should be no less than static
|
|
|
|
rx buffer number if it is not 0.
|
|
|
|
|
|
|
|
config ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM
|
|
|
|
int "Max number of WiFi dynamic TX buffers"
|
|
|
|
depends on WIFI_ENABLED
|
|
|
|
range 16 64
|
|
|
|
default 32
|
|
|
|
help
|
|
|
|
Set the number of WiFi dynamic tx buffers, 0 means no limitation for dynamic tx buffer
|
|
|
|
allocation. The size of dynamic tx buffers is not fixed.
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For each tx packet from high layer stack, WiFi driver make a copy of it. For some applications,
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especially the UDP application, the high layer deliver speed is faster than the WiFi tx
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speed, we may run out of memory if no limitation for the dynamic tx buffer number.
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config ESP32_WIFI_AMPDU_ENABLED
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bool "WiFi AMPDU"
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depends on WIFI_ENABLED
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default y
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help
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Select this option to enable AMPDU feature
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config ESP32_WIFI_NVS_ENABLED
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bool "WiFi NVS flash"
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depends on WIFI_ENABLED
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default y
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help
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Select this option to enable WiFi NVS flash
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2017-01-18 12:05:26 +00:00
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config PHY_ENABLED
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bool
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default y if WIFI_ENABLED || BT_ENABLED
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menu PHY
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visible if PHY_ENABLED
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2017-02-16 14:06:02 +00:00
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2017-02-20 02:23:56 +00:00
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config ESP32_PHY_CALIBRATION_AND_DATA_STORAGE
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bool "Do phy calibration and store calibration data in NVS"
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2017-02-16 14:06:02 +00:00
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depends on PHY_ENABLED
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default y
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help
|
2017-02-20 02:23:56 +00:00
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If this option is enabled, NVS will be initialized and calibration data will be loaded from there.
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PHY calibration will be skipped on deep sleep wakeup. If calibration data is not found, full calibration
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will be performed and stored in NVS. In all other cases, only partial calibration will be performed.
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2017-02-16 14:06:02 +00:00
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If unsure, choose 'y'.
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2017-01-18 12:05:26 +00:00
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2016-11-15 10:36:18 +00:00
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config ESP32_PHY_INIT_DATA_IN_PARTITION
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2017-01-10 05:04:04 +00:00
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bool "Use a partition to store PHY init data"
|
2017-01-18 12:05:26 +00:00
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depends on PHY_ENABLED
|
2017-01-10 05:04:04 +00:00
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default n
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help
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If enabled, PHY init data will be loaded from a partition.
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When using a custom partition table, make sure that PHY data
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partition is included (type: 'data', subtype: 'phy').
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With default partition tables, this is done automatically.
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If PHY init data is stored in a partition, it has to be flashed there,
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otherwise runtime error will occur.
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If this option is not enabled, PHY init data will be embedded
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into the application binary.
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If unsure, choose 'n'.
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2017-01-19 02:58:09 +00:00
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config ESP32_PHY_MAX_WIFI_TX_POWER
|
2017-01-18 12:05:26 +00:00
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int "Max WiFi TX power (dBm)"
|
2017-01-10 05:04:04 +00:00
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range 0 20
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default 20
|
2017-01-18 12:05:26 +00:00
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depends on PHY_ENABLED && WIFI_ENABLED
|
2017-01-10 05:04:04 +00:00
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help
|
2017-01-18 12:05:26 +00:00
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Set maximum transmit power for WiFi radio. Actual transmit power for high
|
2017-01-10 05:04:04 +00:00
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data rates may be lower than this setting.
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2017-01-19 02:58:09 +00:00
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config ESP32_PHY_MAX_TX_POWER
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int
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depends on PHY_ENABLED
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default 20 if !WIFI_ENABLED
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default ESP32_PHY_MAX_WIFI_TX_POWER if WIFI_ENABLED
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2017-01-18 12:05:26 +00:00
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endmenu
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