2016-09-28 15:20:34 +00:00
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <esp_types.h>
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#include "esp_intr.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "freertos/xtensa_api.h"
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#include "soc/dport_reg.h"
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#include "driver/periph_ctrl.h"
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static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
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void periph_module_enable(periph_module_t periph)
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{
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portENTER_CRITICAL(&periph_spinlock);
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switch(periph) {
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2016-11-10 03:23:40 +00:00
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case PERIPH_RMT_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_RMT_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_RMT_RST);
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2016-11-10 03:23:40 +00:00
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break;
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2016-09-28 15:20:34 +00:00
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case PERIPH_LEDC_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_UART0_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_UART1_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART1_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_UART2_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART2_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_I2C0_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT0_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_I2C1_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT1_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT1_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_I2S0_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_I2S1_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_TIMG0_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_TIMG1_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_PWM0_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM0_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM0_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_PWM1_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM1_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM1_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_PWM2_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM2_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM2_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_PWM3_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM3_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM3_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_UHCI0_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI0_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_UHCI1_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI1_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST);
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2016-09-28 15:20:34 +00:00
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break;
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2016-11-21 10:17:07 +00:00
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case PERIPH_PCNT_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PCNT_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PCNT_RST);
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2016-11-21 10:17:07 +00:00
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break;
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2017-01-06 06:20:32 +00:00
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case PERIPH_SPI_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_1);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_1);
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2017-01-06 06:20:32 +00:00
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break;
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case PERIPH_HSPI_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST);
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2017-01-06 06:20:32 +00:00
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break;
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case PERIPH_VSPI_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_2);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_2);
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2017-01-06 06:20:32 +00:00
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break;
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2016-09-28 15:20:34 +00:00
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default:
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break;
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}
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2016-09-29 03:50:25 +00:00
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portEXIT_CRITICAL(&periph_spinlock);
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2016-09-28 15:20:34 +00:00
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}
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void periph_module_disable(periph_module_t periph)
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{
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portENTER_CRITICAL(&periph_spinlock);
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switch(periph) {
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2016-11-23 11:07:30 +00:00
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case PERIPH_RMT_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_RMT_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_RMT_RST);
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2016-11-23 11:07:30 +00:00
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break;
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2016-09-28 15:20:34 +00:00
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case PERIPH_LEDC_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_UART0_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_UART1_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART1_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_UART2_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART2_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_I2C0_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT0_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_I2C1_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT1_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_I2S0_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_I2S1_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_TIMG0_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_TIMG1_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_PWM0_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM0_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM0_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_PWM1_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM1_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM1_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_PWM2_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM2_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM2_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_PWM3_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM3_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM3_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_UHCI0_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI0_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST);
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2016-09-28 15:20:34 +00:00
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break;
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case PERIPH_UHCI1_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI1_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST);
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2016-09-28 15:20:34 +00:00
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break;
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2016-11-23 11:07:30 +00:00
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case PERIPH_PCNT_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PCNT_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PCNT_RST);
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2016-11-23 11:07:30 +00:00
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break;
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2017-01-06 06:20:32 +00:00
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case PERIPH_SPI_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_1);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_1);
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2017-01-06 06:20:32 +00:00
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break;
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case PERIPH_HSPI_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST);
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2017-01-06 06:20:32 +00:00
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break;
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case PERIPH_VSPI_MODULE:
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2017-05-08 12:03:04 +00:00
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_2);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_2);
|
2017-01-06 06:20:32 +00:00
|
|
|
break;
|
2016-09-28 15:20:34 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2016-09-29 03:50:25 +00:00
|
|
|
portEXIT_CRITICAL(&periph_spinlock);
|
2016-09-28 15:20:34 +00:00
|
|
|
}
|