2016-10-08 06:12:55 +00:00
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <esp_types.h>
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#include "esp_err.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/xtensa_api.h"
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#include "driver/gpio.h"
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2016-12-07 06:18:10 +00:00
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#include "driver/rtc_io.h"
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2016-10-08 06:12:55 +00:00
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#include "soc/soc.h"
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2019-06-10 04:08:08 +00:00
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#include "soc/periph_defs.h"
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#include "soc/rtc_cntl_reg.h"
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2018-06-13 04:52:44 +00:00
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#include "soc/gpio_periph.h"
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2019-05-13 10:02:45 +00:00
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#include "esp_log.h"
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2016-10-08 06:12:55 +00:00
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2016-12-07 04:01:30 +00:00
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static const char* GPIO_TAG = "gpio";
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#define GPIO_CHECK(a, str, ret_val) \
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if (!(a)) { \
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ESP_LOGE(GPIO_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
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return (ret_val); \
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}
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2016-10-08 06:12:55 +00:00
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2016-12-24 12:45:57 +00:00
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typedef struct {
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gpio_isr_t fn; /*!< isr function */
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void* args; /*!< isr function args */
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} gpio_isr_func_t;
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static gpio_isr_func_t* gpio_isr_func = NULL;
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static gpio_isr_handle_t gpio_isr_handle;
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static portMUX_TYPE gpio_spinlock = portMUX_INITIALIZER_UNLOCKED;
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esp_err_t gpio_pullup_en(gpio_num_t gpio_num)
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{
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2016-11-15 02:29:52 +00:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2016-12-24 12:45:57 +00:00
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if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
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2016-12-07 06:18:10 +00:00
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rtc_gpio_pullup_en(gpio_num);
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2016-12-24 12:45:57 +00:00
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} else {
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2016-12-08 14:22:10 +00:00
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REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
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2016-12-07 06:18:10 +00:00
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}
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2016-11-15 02:29:52 +00:00
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return ESP_OK;
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}
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2016-12-24 12:45:57 +00:00
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esp_err_t gpio_pullup_dis(gpio_num_t gpio_num)
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{
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2016-11-15 02:29:52 +00:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2016-12-24 12:45:57 +00:00
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if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
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2016-12-07 06:18:10 +00:00
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rtc_gpio_pullup_dis(gpio_num);
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2016-12-24 12:45:57 +00:00
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} else {
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2016-12-07 06:18:10 +00:00
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REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
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}
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2016-11-15 02:29:52 +00:00
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return ESP_OK;
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}
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2016-12-24 12:45:57 +00:00
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esp_err_t gpio_pulldown_en(gpio_num_t gpio_num)
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{
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2016-11-15 02:29:52 +00:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2016-12-24 12:45:57 +00:00
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if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
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2016-12-07 06:18:10 +00:00
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rtc_gpio_pulldown_en(gpio_num);
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2016-12-24 12:45:57 +00:00
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} else {
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REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
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2016-12-07 06:18:10 +00:00
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}
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2016-11-15 02:29:52 +00:00
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return ESP_OK;
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}
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2016-12-24 12:45:57 +00:00
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esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num)
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{
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2016-11-15 02:29:52 +00:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2016-12-24 12:45:57 +00:00
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if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
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rtc_gpio_pulldown_dis(gpio_num);
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} else {
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2016-12-07 06:18:10 +00:00
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REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
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}
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2016-11-15 02:29:52 +00:00
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return ESP_OK;
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}
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2016-12-24 12:45:57 +00:00
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2016-10-08 06:12:55 +00:00
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esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type)
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{
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2016-11-07 06:16:52 +00:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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GPIO_CHECK(intr_type < GPIO_INTR_MAX, "GPIO interrupt type error", ESP_ERR_INVALID_ARG);
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2016-10-08 06:12:55 +00:00
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GPIO.pin[gpio_num].int_type = intr_type;
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return ESP_OK;
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}
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2018-06-04 02:34:23 +00:00
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static void gpio_intr_status_clr(gpio_num_t gpio_num)
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{
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if (gpio_num < 32) {
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GPIO.status_w1tc = BIT(gpio_num);
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} else {
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GPIO.status1_w1tc.intr_st = BIT(gpio_num - 32);
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}
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}
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2017-01-19 12:46:41 +00:00
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static esp_err_t gpio_intr_enable_on_core (gpio_num_t gpio_num, uint32_t core_id)
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2016-10-08 06:12:55 +00:00
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{
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2016-11-07 06:16:52 +00:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2018-06-04 02:34:23 +00:00
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gpio_intr_status_clr(gpio_num);
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2017-01-19 12:46:41 +00:00
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if (core_id == 0) {
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2016-10-08 06:12:55 +00:00
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GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr
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} else {
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GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr
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}
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return ESP_OK;
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}
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2017-01-19 12:46:41 +00:00
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esp_err_t gpio_intr_enable(gpio_num_t gpio_num)
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{
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return gpio_intr_enable_on_core (gpio_num, xPortGetCoreID());
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}
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2016-10-08 06:12:55 +00:00
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esp_err_t gpio_intr_disable(gpio_num_t gpio_num)
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{
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2016-11-07 06:16:52 +00:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2016-10-08 06:12:55 +00:00
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GPIO.pin[gpio_num].int_ena = 0; //disable GPIO intr
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2018-06-04 02:34:23 +00:00
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gpio_intr_status_clr(gpio_num);
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2016-10-08 06:12:55 +00:00
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return ESP_OK;
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}
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static esp_err_t gpio_output_disable(gpio_num_t gpio_num)
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{
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2016-11-07 06:16:52 +00:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2016-12-07 06:18:10 +00:00
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if (gpio_num < 32) {
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2016-10-08 06:12:55 +00:00
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GPIO.enable_w1tc = (0x1 << gpio_num);
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} else {
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GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32));
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}
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2017-06-26 02:41:40 +00:00
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// Ensure no other output signal is routed via GPIO matrix to this pin
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REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4),
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SIG_GPIO_OUT_IDX);
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2016-10-08 06:12:55 +00:00
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return ESP_OK;
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}
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static esp_err_t gpio_output_enable(gpio_num_t gpio_num)
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{
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2016-11-07 06:16:52 +00:00
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GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG);
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2016-12-07 06:18:10 +00:00
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if (gpio_num < 32) {
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2016-10-08 06:12:55 +00:00
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GPIO.enable_w1ts = (0x1 << gpio_num);
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} else {
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GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32));
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}
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2017-06-26 02:41:40 +00:00
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gpio_matrix_out(gpio_num, SIG_GPIO_OUT_IDX, false, false);
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2016-10-08 06:12:55 +00:00
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return ESP_OK;
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}
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esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level)
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{
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2016-12-22 02:05:19 +00:00
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GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG);
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2016-12-07 06:18:10 +00:00
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if (level) {
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if (gpio_num < 32) {
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2016-10-08 06:12:55 +00:00
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GPIO.out_w1ts = (1 << gpio_num);
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} else {
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GPIO.out1_w1ts.data = (1 << (gpio_num - 32));
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}
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} else {
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2016-12-07 06:18:10 +00:00
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if (gpio_num < 32) {
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2016-10-08 06:12:55 +00:00
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GPIO.out_w1tc = (1 << gpio_num);
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} else {
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GPIO.out1_w1tc.data = (1 << (gpio_num - 32));
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}
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}
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return ESP_OK;
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}
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int gpio_get_level(gpio_num_t gpio_num)
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{
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2016-12-07 06:18:10 +00:00
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if (gpio_num < 32) {
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2016-10-08 06:12:55 +00:00
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return (GPIO.in >> gpio_num) & 0x1;
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} else {
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return (GPIO.in1.data >> (gpio_num - 32)) & 0x1;
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}
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}
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esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull)
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{
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2016-11-07 06:16:52 +00:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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GPIO_CHECK(pull <= GPIO_FLOATING, "GPIO pull mode error", ESP_ERR_INVALID_ARG);
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2016-10-08 06:12:55 +00:00
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esp_err_t ret = ESP_OK;
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2016-12-07 06:18:10 +00:00
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switch (pull) {
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case GPIO_PULLUP_ONLY:
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gpio_pulldown_dis(gpio_num);
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gpio_pullup_en(gpio_num);
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break;
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case GPIO_PULLDOWN_ONLY:
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gpio_pulldown_en(gpio_num);
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gpio_pullup_dis(gpio_num);
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break;
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case GPIO_PULLUP_PULLDOWN:
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gpio_pulldown_en(gpio_num);
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gpio_pullup_en(gpio_num);
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break;
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case GPIO_FLOATING:
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gpio_pulldown_dis(gpio_num);
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gpio_pullup_dis(gpio_num);
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break;
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default:
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ESP_LOGE(GPIO_TAG, "Unknown pull up/down mode,gpio_num=%u,pull=%u", gpio_num, pull);
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ret = ESP_ERR_INVALID_ARG;
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break;
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2016-10-08 06:12:55 +00:00
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}
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return ret;
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}
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esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode)
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{
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2016-11-07 06:16:52 +00:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2019-06-06 02:57:29 +00:00
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#if CONFIG_IDF_TARGET_ESP32
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2017-11-21 07:06:32 +00:00
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if (gpio_num >= 34 && (mode & GPIO_MODE_DEF_OUTPUT)) {
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2019-06-06 02:57:29 +00:00
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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if (gpio_num >= 46 && (mode & GPIO_MODE_DEF_OUTPUT)) {
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#endif
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2016-12-07 06:18:10 +00:00
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ESP_LOGE(GPIO_TAG, "io_num=%d can only be input", gpio_num);
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2016-10-08 06:12:55 +00:00
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return ESP_ERR_INVALID_ARG;
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}
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esp_err_t ret = ESP_OK;
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2016-12-07 06:18:10 +00:00
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if (mode & GPIO_MODE_DEF_INPUT) {
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2016-10-08 06:12:55 +00:00
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
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} else {
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
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}
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2016-12-07 06:18:10 +00:00
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if (mode & GPIO_MODE_DEF_OUTPUT) {
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2017-06-26 02:41:40 +00:00
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gpio_output_enable(gpio_num);
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2016-10-08 06:12:55 +00:00
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} else {
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2017-06-26 02:41:40 +00:00
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gpio_output_disable(gpio_num);
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2016-10-08 06:12:55 +00:00
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}
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2016-12-07 06:18:10 +00:00
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if (mode & GPIO_MODE_DEF_OD) {
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2016-10-08 06:12:55 +00:00
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GPIO.pin[gpio_num].pad_driver = 1;
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} else {
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GPIO.pin[gpio_num].pad_driver = 0;
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}
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return ret;
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}
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2017-04-13 17:33:33 +00:00
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esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
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2016-10-08 06:12:55 +00:00
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{
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uint64_t gpio_pin_mask = (pGPIOConfig->pin_bit_mask);
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uint32_t io_reg = 0;
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uint32_t io_num = 0;
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2016-11-07 06:16:52 +00:00
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uint8_t input_en = 0;
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uint8_t output_en = 0;
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uint8_t od_en = 0;
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uint8_t pu_en = 0;
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uint8_t pd_en = 0;
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2016-12-07 06:18:10 +00:00
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if (pGPIOConfig->pin_bit_mask == 0 || pGPIOConfig->pin_bit_mask >= (((uint64_t) 1) << GPIO_PIN_COUNT)) {
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2016-11-07 06:16:52 +00:00
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ESP_LOGE(GPIO_TAG, "GPIO_PIN mask error ");
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2016-10-08 06:12:55 +00:00
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return ESP_ERR_INVALID_ARG;
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}
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2016-12-07 06:18:10 +00:00
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if ((pGPIOConfig->mode) & (GPIO_MODE_DEF_OUTPUT)) {
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2016-10-08 06:12:55 +00:00
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//GPIO 34/35/36/37/38/39 can only be used as input mode;
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2016-12-07 06:18:10 +00:00
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if ((gpio_pin_mask & ( GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) {
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2016-11-07 06:16:52 +00:00
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ESP_LOGE(GPIO_TAG, "GPIO34-39 can only be used as input mode");
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2016-10-08 06:12:55 +00:00
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return ESP_ERR_INVALID_ARG;
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}
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}
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do {
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io_reg = GPIO_PIN_MUX_REG[io_num];
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2018-06-04 02:34:23 +00:00
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if (((gpio_pin_mask >> io_num) & BIT(0))) {
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|
|
|
if (!io_reg) {
|
|
|
|
ESP_LOGE(GPIO_TAG, "IO%d is not a valid GPIO",io_num);
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
2016-12-07 06:18:10 +00:00
|
|
|
if(RTC_GPIO_IS_VALID_GPIO(io_num)){
|
|
|
|
rtc_gpio_deinit(io_num);
|
|
|
|
}
|
|
|
|
if ((pGPIOConfig->mode) & GPIO_MODE_DEF_INPUT) {
|
2016-11-07 06:16:52 +00:00
|
|
|
input_en = 1;
|
2016-10-08 06:12:55 +00:00
|
|
|
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[io_num]);
|
|
|
|
} else {
|
|
|
|
PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[io_num]);
|
|
|
|
}
|
2016-12-07 06:18:10 +00:00
|
|
|
if ((pGPIOConfig->mode) & GPIO_MODE_DEF_OD) {
|
2016-11-07 06:16:52 +00:00
|
|
|
od_en = 1;
|
2016-10-08 06:12:55 +00:00
|
|
|
GPIO.pin[io_num].pad_driver = 1; /*0x01 Open-drain */
|
|
|
|
} else {
|
|
|
|
GPIO.pin[io_num].pad_driver = 0; /*0x00 Normal gpio output */
|
|
|
|
}
|
2016-12-07 06:18:10 +00:00
|
|
|
if ((pGPIOConfig->mode) & GPIO_MODE_DEF_OUTPUT) {
|
2016-11-07 06:16:52 +00:00
|
|
|
output_en = 1;
|
2016-10-08 06:12:55 +00:00
|
|
|
gpio_output_enable(io_num);
|
|
|
|
} else {
|
|
|
|
gpio_output_disable(io_num);
|
|
|
|
}
|
2016-12-07 06:18:10 +00:00
|
|
|
if (pGPIOConfig->pull_up_en) {
|
2016-11-07 06:16:52 +00:00
|
|
|
pu_en = 1;
|
2016-12-07 06:18:10 +00:00
|
|
|
gpio_pullup_en(io_num);
|
2016-10-08 06:12:55 +00:00
|
|
|
} else {
|
2016-12-07 06:18:10 +00:00
|
|
|
gpio_pullup_dis(io_num);
|
2016-10-08 06:12:55 +00:00
|
|
|
}
|
2016-12-07 06:18:10 +00:00
|
|
|
if (pGPIOConfig->pull_down_en) {
|
2016-11-07 06:16:52 +00:00
|
|
|
pd_en = 1;
|
2016-12-07 06:18:10 +00:00
|
|
|
gpio_pulldown_en(io_num);
|
2016-10-08 06:12:55 +00:00
|
|
|
} else {
|
2016-12-07 06:18:10 +00:00
|
|
|
gpio_pulldown_dis(io_num);
|
2016-10-08 06:12:55 +00:00
|
|
|
}
|
2016-11-07 06:16:52 +00:00
|
|
|
ESP_LOGI(GPIO_TAG, "GPIO[%d]| InputEn: %d| OutputEn: %d| OpenDrain: %d| Pullup: %d| Pulldown: %d| Intr:%d ", io_num, input_en, output_en, od_en, pu_en, pd_en, pGPIOConfig->intr_type);
|
2016-10-08 06:12:55 +00:00
|
|
|
gpio_set_intr_type(io_num, pGPIOConfig->intr_type);
|
2016-12-07 06:18:10 +00:00
|
|
|
if (pGPIOConfig->intr_type) {
|
2016-10-08 06:12:55 +00:00
|
|
|
gpio_intr_enable(io_num);
|
|
|
|
} else {
|
|
|
|
gpio_intr_disable(io_num);
|
|
|
|
}
|
|
|
|
PIN_FUNC_SELECT(io_reg, PIN_FUNC_GPIO); /*function number 2 is GPIO_FUNC for each pin */
|
|
|
|
}
|
|
|
|
io_num++;
|
2016-12-07 06:18:10 +00:00
|
|
|
} while (io_num < GPIO_PIN_COUNT);
|
2016-10-08 06:12:55 +00:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2018-06-08 07:33:04 +00:00
|
|
|
esp_err_t gpio_reset_pin(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
assert(gpio_num >= 0 && GPIO_IS_VALID_GPIO(gpio_num));
|
|
|
|
gpio_config_t cfg = {
|
2018-08-08 12:31:17 +00:00
|
|
|
.pin_bit_mask = BIT64(gpio_num),
|
2018-06-08 07:33:04 +00:00
|
|
|
.mode = GPIO_MODE_DISABLE,
|
|
|
|
//for powersave reasons, the GPIO should not be floating, select pullup
|
|
|
|
.pull_up_en = true,
|
|
|
|
.pull_down_en = false,
|
|
|
|
.intr_type = GPIO_INTR_DISABLE,
|
|
|
|
};
|
|
|
|
gpio_config(&cfg);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2018-12-21 14:07:51 +00:00
|
|
|
static inline void IRAM_ATTR gpio_isr_loop(uint32_t status, const uint32_t gpio_num_start) {
|
|
|
|
while (status) {
|
|
|
|
int nbit = __builtin_ffs(status) - 1;
|
|
|
|
status &= ~(1 << nbit);
|
|
|
|
int gpio_num = gpio_num_start + nbit;
|
|
|
|
if (gpio_isr_func[gpio_num].fn != NULL) {
|
|
|
|
gpio_isr_func[gpio_num].fn(gpio_isr_func[gpio_num].args);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void IRAM_ATTR gpio_intr_service(void* arg)
|
2016-12-24 12:45:57 +00:00
|
|
|
{
|
|
|
|
//GPIO intr process
|
|
|
|
if (gpio_isr_func == NULL) {
|
|
|
|
return;
|
|
|
|
}
|
2018-12-21 14:07:51 +00:00
|
|
|
|
|
|
|
//read status to get interrupt status for GPIO0-31
|
|
|
|
const uint32_t gpio_intr_status = GPIO.status;
|
|
|
|
if (gpio_intr_status) {
|
|
|
|
gpio_isr_loop(gpio_intr_status, 0);
|
|
|
|
GPIO.status_w1tc = gpio_intr_status;
|
|
|
|
}
|
|
|
|
|
|
|
|
//read status1 to get interrupt status for GPIO32-39
|
|
|
|
const uint32_t gpio_intr_status_h = GPIO.status1.intr_st;
|
|
|
|
if (gpio_intr_status_h) {
|
|
|
|
gpio_isr_loop(gpio_intr_status_h, 32);
|
|
|
|
GPIO.status1_w1tc.intr_st = gpio_intr_status_h;
|
|
|
|
}
|
2016-12-24 12:45:57 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_isr_handler_add(gpio_num_t gpio_num, gpio_isr_t isr_handler, void* args)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(gpio_isr_func != NULL, "GPIO isr service is not installed, call gpio_install_isr_service() first", ESP_ERR_INVALID_STATE);
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
portENTER_CRITICAL(&gpio_spinlock);
|
|
|
|
gpio_intr_disable(gpio_num);
|
|
|
|
if (gpio_isr_func) {
|
|
|
|
gpio_isr_func[gpio_num].fn = isr_handler;
|
|
|
|
gpio_isr_func[gpio_num].args = args;
|
|
|
|
}
|
2017-01-19 12:46:41 +00:00
|
|
|
gpio_intr_enable_on_core (gpio_num, esp_intr_get_cpu(gpio_isr_handle));
|
2016-12-24 12:45:57 +00:00
|
|
|
portEXIT_CRITICAL(&gpio_spinlock);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_isr_handler_remove(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(gpio_isr_func != NULL, "GPIO isr service is not installed, call gpio_install_isr_service() first", ESP_ERR_INVALID_STATE);
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
portENTER_CRITICAL(&gpio_spinlock);
|
|
|
|
gpio_intr_disable(gpio_num);
|
|
|
|
if (gpio_isr_func) {
|
|
|
|
gpio_isr_func[gpio_num].fn = NULL;
|
|
|
|
gpio_isr_func[gpio_num].args = NULL;
|
|
|
|
}
|
|
|
|
portEXIT_CRITICAL(&gpio_spinlock);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_install_isr_service(int intr_alloc_flags)
|
|
|
|
{
|
2018-03-26 02:50:22 +00:00
|
|
|
GPIO_CHECK(gpio_isr_func == NULL, "GPIO isr service already installed", ESP_ERR_INVALID_STATE);
|
2016-12-24 12:45:57 +00:00
|
|
|
esp_err_t ret;
|
|
|
|
portENTER_CRITICAL(&gpio_spinlock);
|
|
|
|
gpio_isr_func = (gpio_isr_func_t*) calloc(GPIO_NUM_MAX, sizeof(gpio_isr_func_t));
|
|
|
|
if (gpio_isr_func == NULL) {
|
|
|
|
ret = ESP_ERR_NO_MEM;
|
|
|
|
} else {
|
|
|
|
ret = gpio_isr_register(gpio_intr_service, NULL, intr_alloc_flags, &gpio_isr_handle);
|
|
|
|
}
|
|
|
|
portEXIT_CRITICAL(&gpio_spinlock);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void gpio_uninstall_isr_service()
|
|
|
|
{
|
|
|
|
if (gpio_isr_func == NULL) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
portENTER_CRITICAL(&gpio_spinlock);
|
|
|
|
esp_intr_free(gpio_isr_handle);
|
|
|
|
free(gpio_isr_func);
|
|
|
|
gpio_isr_func = NULL;
|
|
|
|
portEXIT_CRITICAL(&gpio_spinlock);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-12-07 13:30:21 +00:00
|
|
|
esp_err_t gpio_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags, gpio_isr_handle_t *handle)
|
2016-10-08 06:12:55 +00:00
|
|
|
{
|
2016-11-07 06:16:52 +00:00
|
|
|
GPIO_CHECK(fn, "GPIO ISR null", ESP_ERR_INVALID_ARG);
|
2016-12-07 13:30:21 +00:00
|
|
|
return esp_intr_alloc(ETS_GPIO_INTR_SOURCE, intr_alloc_flags, fn, arg, handle);
|
2016-10-08 06:12:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
|
|
|
|
{
|
2016-11-07 06:16:52 +00:00
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
2016-10-08 06:12:55 +00:00
|
|
|
esp_err_t ret = ESP_OK;
|
2016-12-24 12:45:57 +00:00
|
|
|
if (( intr_type == GPIO_INTR_LOW_LEVEL ) || ( intr_type == GPIO_INTR_HIGH_LEVEL )) {
|
2018-08-13 22:57:32 +00:00
|
|
|
if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
|
|
|
|
ret = rtc_gpio_wakeup_enable(gpio_num, intr_type);
|
|
|
|
} else {
|
|
|
|
GPIO.pin[gpio_num].int_type = intr_type;
|
|
|
|
GPIO.pin[gpio_num].wakeup_enable = 0x1;
|
|
|
|
}
|
2016-10-08 06:12:55 +00:00
|
|
|
} else {
|
2018-08-13 22:57:32 +00:00
|
|
|
ESP_LOGE(GPIO_TAG, "GPIO wakeup only supports level mode, but edge mode set. gpio_num:%u", gpio_num);
|
2016-10-08 06:12:55 +00:00
|
|
|
ret = ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num)
|
|
|
|
{
|
2016-11-07 06:16:52 +00:00
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
2016-10-08 06:12:55 +00:00
|
|
|
GPIO.pin[gpio_num].wakeup_enable = 0;
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
2017-07-17 07:38:19 +00:00
|
|
|
|
|
|
|
esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t strength)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
GPIO_CHECK(strength < GPIO_DRIVE_CAP_MAX, "GPIO drive capability error", ESP_ERR_INVALID_ARG);
|
|
|
|
|
|
|
|
if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
|
|
|
|
rtc_gpio_set_drive_capability(gpio_num, strength);
|
|
|
|
} else {
|
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S);
|
|
|
|
}
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* strength)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
GPIO_CHECK(strength != NULL, "GPIO drive capability pointer error", ESP_ERR_INVALID_ARG);
|
|
|
|
|
|
|
|
if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
|
|
|
|
return rtc_gpio_get_drive_capability(gpio_num, strength);
|
|
|
|
} else {
|
|
|
|
*strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
|
|
|
|
}
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
2018-04-03 14:09:30 +00:00
|
|
|
|
|
|
|
static const uint32_t GPIO_HOLD_MASK[34] = {
|
|
|
|
0,
|
|
|
|
GPIO_SEL_1,
|
|
|
|
0,
|
|
|
|
GPIO_SEL_0,
|
|
|
|
0,
|
|
|
|
GPIO_SEL_8,
|
|
|
|
GPIO_SEL_2,
|
|
|
|
GPIO_SEL_3,
|
|
|
|
GPIO_SEL_4,
|
|
|
|
GPIO_SEL_5,
|
|
|
|
GPIO_SEL_6,
|
|
|
|
GPIO_SEL_7,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
GPIO_SEL_9,
|
|
|
|
GPIO_SEL_10,
|
|
|
|
GPIO_SEL_11,
|
|
|
|
GPIO_SEL_12,
|
|
|
|
0,
|
|
|
|
GPIO_SEL_14,
|
|
|
|
GPIO_SEL_15,
|
|
|
|
GPIO_SEL_16,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
};
|
|
|
|
|
|
|
|
esp_err_t gpio_hold_en(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Only output-capable GPIO support this function", ESP_ERR_NOT_SUPPORTED);
|
|
|
|
esp_err_t r = ESP_OK;
|
|
|
|
if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
|
|
|
|
r = rtc_gpio_hold_en(gpio_num);
|
|
|
|
} else if (GPIO_HOLD_MASK[gpio_num]) {
|
2019-06-06 02:57:29 +00:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
2018-04-03 14:09:30 +00:00
|
|
|
SET_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
|
2019-06-06 02:57:29 +00:00
|
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
|
|
SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
|
|
|
|
#endif
|
2018-04-03 14:09:30 +00:00
|
|
|
} else {
|
|
|
|
r = ESP_ERR_NOT_SUPPORTED;
|
|
|
|
}
|
|
|
|
return r == ESP_OK ? ESP_OK : ESP_ERR_NOT_SUPPORTED;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_hold_dis(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Only output-capable GPIO support this function", ESP_ERR_NOT_SUPPORTED);
|
|
|
|
esp_err_t r = ESP_OK;
|
|
|
|
if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
|
|
|
|
r = rtc_gpio_hold_dis(gpio_num);
|
|
|
|
} else if (GPIO_HOLD_MASK[gpio_num]) {
|
2019-06-06 02:57:29 +00:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
2018-04-03 14:09:30 +00:00
|
|
|
CLEAR_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
|
2019-06-06 02:57:29 +00:00
|
|
|
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
|
|
|
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
|
|
|
|
#endif
|
2018-04-03 14:09:30 +00:00
|
|
|
} else {
|
|
|
|
r = ESP_ERR_NOT_SUPPORTED;
|
|
|
|
}
|
|
|
|
return r == ESP_OK ? ESP_OK : ESP_ERR_NOT_SUPPORTED;
|
2018-04-23 17:23:12 +00:00
|
|
|
}
|
|
|
|
|
2018-12-07 13:44:43 +00:00
|
|
|
void gpio_deep_sleep_hold_en(void)
|
|
|
|
{
|
|
|
|
portENTER_CRITICAL(&gpio_spinlock);
|
|
|
|
SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
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portEXIT_CRITICAL(&gpio_spinlock);
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}
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void gpio_deep_sleep_hold_dis(void)
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{
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portENTER_CRITICAL(&gpio_spinlock);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
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portEXIT_CRITICAL(&gpio_spinlock);
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}
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2018-04-23 17:23:12 +00:00
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void gpio_iomux_in(uint32_t gpio, uint32_t signal_idx)
|
|
|
|
{
|
|
|
|
GPIO.func_in_sel_cfg[signal_idx].sig_in_sel = 0;
|
|
|
|
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]);
|
|
|
|
}
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void gpio_iomux_out(uint8_t gpio_num, int func, bool oen_inv)
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|
|
|
{
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|
|
|
GPIO.func_out_sel_cfg[gpio_num].oen_sel = 0;
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|
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GPIO.func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
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|
|
|
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func);
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|
|
|
}
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