37 lines
1.1 KiB
C
37 lines
1.1 KiB
C
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_CPU_H
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#define _SOC_CPU_H
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#include "xtensa/corebits.h"
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/* C macros for xtensa special register read/write/exchange */
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#define RSR(reg, curval) asm volatile ("rsr %0, " #reg : "=r" (curval));
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#define WSR(reg, newval) asm volatile ("wsr %0, " #reg : : "r" (newval));
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#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval));
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/* Return true if the CPU is in an interrupt context
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(PS.UM == 0)
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*/
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static inline bool cpu_in_interrupt_context(void)
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{
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uint32_t ps;
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RSR(PS, ps);
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return (ps & PS_UM) == 0;
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}
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#endif
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