235 lines
9.5 KiB
C
235 lines
9.5 KiB
C
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp_efuse_utility.h"
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#include "soc/efuse_periph.h"
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#include "esp32/clk.h"
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#include "esp_log.h"
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#include "assert.h"
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#include "sdkconfig.h"
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#include <sys/param.h>
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static const char *TAG = "efuse";
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#ifdef CONFIG_EFUSE_VIRTUAL
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extern uint32_t virt_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK];
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#endif // CONFIG_EFUSE_VIRTUAL
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/*Range addresses to read blocks*/
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const esp_efuse_range_addr_t range_read_addr_blocks[] = {
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{EFUSE_BLK0_RDATA0_REG, EFUSE_BLK0_RDATA6_REG}, // range address of EFUSE_BLK0
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{EFUSE_BLK1_RDATA0_REG, EFUSE_BLK1_RDATA7_REG}, // range address of EFUSE_BLK1
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{EFUSE_BLK2_RDATA0_REG, EFUSE_BLK2_RDATA7_REG}, // range address of EFUSE_BLK2
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{EFUSE_BLK3_RDATA0_REG, EFUSE_BLK3_RDATA7_REG} // range address of EFUSE_BLK3
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};
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/*Range addresses to write blocks*/
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const esp_efuse_range_addr_t range_write_addr_blocks[] = {
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{EFUSE_BLK0_WDATA0_REG, EFUSE_BLK0_WDATA6_REG}, // range address of EFUSE_BLK0
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{EFUSE_BLK1_WDATA0_REG, EFUSE_BLK1_WDATA7_REG}, // range address of EFUSE_BLK1
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{EFUSE_BLK2_WDATA0_REG, EFUSE_BLK2_WDATA7_REG}, // range address of EFUSE_BLK2
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{EFUSE_BLK3_WDATA0_REG, EFUSE_BLK3_WDATA7_REG} // range address of EFUSE_BLK3
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};
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#define EFUSE_CONF_WRITE 0x5A5A /* eFuse_pgm_op_ena, force no rd/wr disable. */
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#define EFUSE_CONF_READ 0x5AA5 /* eFuse_read_op_ena, release force. */
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#define EFUSE_CMD_PGM 0x02 /* Command to program. */
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#define EFUSE_CMD_READ 0x01 /* Command to read. */
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#ifndef CONFIG_EFUSE_VIRTUAL
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// Update Efuse timing configuration
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static esp_err_t esp_efuse_set_timing(void)
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{
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uint32_t apb_freq_mhz = esp_clk_apb_freq() / 1000000;
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uint32_t clk_sel0, clk_sel1, dac_clk_div;
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if (apb_freq_mhz <= 26) {
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clk_sel0 = 250;
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clk_sel1 = 255;
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dac_clk_div = 52;
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} else if (apb_freq_mhz <= 40) {
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clk_sel0 = 160;
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clk_sel1 = 255;
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dac_clk_div = 80;
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} else {
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clk_sel0 = 80;
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clk_sel1 = 128;
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dac_clk_div = 100;
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}
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REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, dac_clk_div);
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REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, clk_sel0);
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REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, clk_sel1);
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return ESP_OK;
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}
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#endif // ifndef CONFIG_EFUSE_VIRTUAL
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// Efuse read operation: copies data from physical efuses to efuse read registers.
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void esp_efuse_utility_clear_program_registers(void)
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{
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REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ);
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}
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// Burn values written to the efuse write registers
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void esp_efuse_utility_burn_efuses(void)
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{
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#ifdef CONFIG_EFUSE_VIRTUAL
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ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
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for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
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esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(num_block);
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if (scheme == EFUSE_CODING_SCHEME_3_4) {
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uint8_t buf[COUNT_EFUSE_REG_PER_BLOCK * 4] = { 0 };
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int i = 0;
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for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4, ++i) {
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*((uint32_t*)buf + i) = REG_READ(addr_wr_block);
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}
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int j = 0;
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uint32_t out_buf[COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
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for (int k = 0; k < 4; ++k, ++j) {
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memcpy((uint8_t*)out_buf + j * 6, &buf[k * 8], 6);
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}
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for (int k = 0; k < COUNT_EFUSE_REG_PER_BLOCK; ++k) {
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REG_WRITE(range_write_addr_blocks[num_block].start + k * 4, out_buf[k]);
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}
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}
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int subblock = 0;
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for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
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virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
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}
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}
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#else
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esp_efuse_set_timing();
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// Permanently update values written to the efuse write registers
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REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_WRITE);
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REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_PGM);
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while (REG_READ(EFUSE_CMD_REG) != 0) {};
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REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ);
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REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_READ);
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while (REG_READ(EFUSE_CMD_REG) != 0) {};
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#endif // CONFIG_EFUSE_VIRTUAL
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esp_efuse_utility_reset();
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}
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esp_err_t esp_efuse_utility_apply_34_encoding(const uint8_t *in_bytes, uint32_t *out_words, size_t in_bytes_len)
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{
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if (in_bytes == NULL || out_words == NULL || in_bytes_len % 6 != 0) {
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return ESP_ERR_INVALID_ARG;
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}
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while (in_bytes_len > 0) {
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uint8_t out[8];
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uint8_t xor = 0;
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uint8_t mul = 0;
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for (int i = 0; i < 6; i++) {
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xor ^= in_bytes[i];
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mul += (i + 1) * __builtin_popcount(in_bytes[i]);
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}
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memcpy(out, in_bytes, 6); // Data bytes
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out[6] = xor;
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out[7] = mul;
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memcpy(out_words, out, 8);
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in_bytes_len -= 6;
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in_bytes += 6;
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out_words += 2;
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}
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return ESP_OK;
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}
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static bool read_w_data_and_check_fill(esp_efuse_block_t num_block, uint32_t *buf_w_data)
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{
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bool blk_is_filled = false;
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int i = 0;
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for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4, ++i) {
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buf_w_data[i] = REG_READ(addr_wr_block);
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if (buf_w_data[i] != 0) {
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REG_WRITE(addr_wr_block, 0);
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blk_is_filled = true;
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}
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}
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return blk_is_filled;
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}
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static void read_r_data(esp_efuse_block_t num_block, uint32_t* buf_r_data)
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{
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int i = 0;
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for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++i) {
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buf_r_data[i] = esp_efuse_utility_read_reg(num_block, i);
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}
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}
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// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
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// This function reads EFUSE_BLKx_WDATAx_REG registers, applies coding scheme and writes encoded values back to EFUSE_BLKx_WDATAx_REG.
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esp_err_t esp_efuse_utility_apply_new_coding_scheme()
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{
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uint8_t buf_w_data[COUNT_EFUSE_REG_PER_BLOCK * 4];
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uint8_t buf_r_data[COUNT_EFUSE_REG_PER_BLOCK * 4];
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uint32_t reg[COUNT_EFUSE_REG_PER_BLOCK];
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// start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
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for (int num_block = 1; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
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esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(num_block);
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// check and apply a new coding scheme.
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if (scheme != EFUSE_CODING_SCHEME_NONE) {
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memset(buf_w_data, 0, sizeof(buf_w_data));
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memset((uint8_t*)reg, 0, sizeof(reg));
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if (read_w_data_and_check_fill(num_block, (uint32_t*)buf_w_data) == true) {
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read_r_data(num_block, (uint32_t*)buf_r_data);
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if (scheme == EFUSE_CODING_SCHEME_3_4) {
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if (*((uint32_t*)buf_w_data + 6) != 0 || *((uint32_t*)buf_w_data + 7) != 0) {
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return ESP_ERR_CODING;
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}
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for (int i = 0; i < 24; ++i) {
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if (buf_w_data[i] != 0) {
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int st_offset_buf = (i / 6) * 6;
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// check that place is free.
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for (int n = st_offset_buf; n < st_offset_buf + 6; ++n) {
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if (buf_r_data[n] != 0) {
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ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
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return ESP_ERR_CODING;
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}
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}
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esp_err_t err = esp_efuse_utility_apply_34_encoding(&buf_w_data[st_offset_buf], reg, 6);
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if (err != ESP_OK) {
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return err;
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}
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int num_reg = (st_offset_buf / 6) * 2;
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for (int r = 0; r < 2; r++) {
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REG_WRITE(range_write_addr_blocks[num_block].start + (num_reg + r) * 4, reg[r]);
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}
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i = st_offset_buf + 5;
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}
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}
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} else if (scheme == EFUSE_CODING_SCHEME_REPEAT) {
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uint32_t* buf_32 = (uint32_t*)buf_w_data;
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for (int i = 4; i < 8; ++i) {
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if (*(buf_32 + i) != 0) {
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return ESP_ERR_CODING;
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}
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}
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for (int i = 0; i < 4; ++i) {
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if (buf_32[i] != 0) {
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REG_WRITE(range_write_addr_blocks[num_block].start + i * 4, buf_32[i]);
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REG_WRITE(range_write_addr_blocks[num_block].start + (i + 4) * 4, buf_32[i]);
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}
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}
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}
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}
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}
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}
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return ESP_OK;
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}
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