400 lines
16 KiB
C
400 lines
16 KiB
C
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_SPI_REG_H_
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#define _SOC_SPI_REG_H_
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#include "soc.h"
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#define SPI_CMD( i ) (REG_SPI_BASE( i ) + 0x0)
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#define SPI_FLASH_READ (BIT(31))
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#define SPI_FLASH_WREN (BIT(30))
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#define SPI_FLASH_WRDI (BIT(29))
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#define SPI_FLASH_RDID (BIT(28))
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#define SPI_FLASH_RDSR (BIT(27))
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#define SPI_FLASH_WRSR (BIT(26))
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#define SPI_FLASH_PP (BIT(25))
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#define SPI_FLASH_SE (BIT(24))
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#define SPI_FLASH_BE (BIT(23))
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#define SPI_FLASH_CE (BIT(22))
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#define SPI_FLASH_DP (BIT(21))
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#define SPI_FLASH_RES (BIT(20))
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#define SPI_FLASH_HPM (BIT(19))
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#define SPI_USR (BIT(18))
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#define SPI_FLASH_PES (BIT(17))
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#define SPI_FLASH_PER (BIT(16))
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#define SPI_ADDR( i ) (REG_SPI_BASE( i ) + 0x4)
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#define SPI_CTRL( i ) (REG_SPI_BASE( i ) + 0x8)
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#define SPI_WR_BIT_ORDER (BIT(26))
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#define SPI_RD_BIT_ORDER (BIT(25))
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#define SPI_FREAD_QIO (BIT(24))
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#define SPI_FREAD_DIO (BIT(23))
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#define SPI_WRSR_2B (BIT(22))
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#define SPI_WP_REG (BIT(21))
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#define SPI_FREAD_QUAD (BIT(20))
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#define SPI_RESANDRES (BIT(15))
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#define SPI_FREAD_DUAL (BIT(14))
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#define SPI_FASTRD_MODE (BIT(13))
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#define SPI_WAIT_FLASH_IDLE_EN (BIT(12))
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#define SPI_TX_CRC_EN (BIT(11))
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#define SPI_FCS_CRC_EN (BIT(10))
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#define SPI_CTRL1( i ) (REG_SPI_BASE( i ) + 0xC)
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#define SPI_CS_HOLD_DELAY 0x0000000F
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#define SPI_CS_HOLD_DELAY_S 28
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#define SPI_CS_HOLD_DELAY_RES 0x00000FFF
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#define SPI_CS_HOLD_DELAY_RES_S 16
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#define SPI_RD_STATUS( i ) (REG_SPI_BASE( i ) + 0x10)
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#define SPI_STATUS_EXT 0x000000FF
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#define SPI_STATUS_EXT_S 24
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#define SPI_WB_MODE 0x000000FF
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#define SPI_WB_MODE_S 16
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#define SPI_STATUS 0x0000FFFF
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#define SPI_STATUS_S 0
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#define SPI_CTRL2( i ) (REG_SPI_BASE( i ) + 0x14)
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#define SPI_CS_DELAY_NUM 0x0000000F
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#define SPI_CS_DELAY_NUM_S 28
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#define SPI_CS_DELAY_MODE 0x00000003
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#define SPI_CS_DELAY_MODE_S 26
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#define SPI_MOSI_DELAY_NUM 0x00000007
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#define SPI_MOSI_DELAY_NUM_S 23
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#define SPI_MOSI_DELAY_MODE 0x00000003
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#define SPI_MOSI_DELAY_MODE_S 21
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#define SPI_MISO_DELAY_NUM 0x00000007
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#define SPI_MISO_DELAY_NUM_S 18
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#define SPI_MISO_DELAY_MODE 0x00000003
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#define SPI_MISO_DELAY_MODE_S 16
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#define SPI_CK_OUT_HIGH_MODE 0x0000000F
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#define SPI_CK_OUT_HIGH_MODE_S 12
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#define SPI_CK_OUT_LOW_MODE 0x0000000F
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#define SPI_CK_OUT_LOW_MODE_S 8
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#define SPI_HOLD_TIME 0x0000000F
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#define SPI_HOLD_TIME_S 4
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#define SPI_SETUP_TIME 0x0000000F
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#define SPI_SETUP_TIME_S 0
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#define SPI_CLOCK( i ) (REG_SPI_BASE( i ) + 0x18)
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#define SPI_CLK_EQU_SYSCLK (BIT(31))
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#define SPI_CLKDIV_PRE 0x00001FFF
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#define SPI_CLKDIV_PRE_S 18
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#define SPI_CLKCNT_N 0x0000003F
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#define SPI_CLKCNT_N_S 12
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#define SPI_CLKCNT_H 0x0000003F
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#define SPI_CLKCNT_H_S 6
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#define SPI_CLKCNT_L 0x0000003F
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#define SPI_CLKCNT_L_S 0
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#define SPI_USER( i ) (REG_SPI_BASE( i ) + 0x1C)
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#define SPI_USR_COMMAND (BIT(31))
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#define SPI_USR_ADDR (BIT(30))
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#define SPI_USR_DUMMY (BIT(29))
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#define SPI_USR_MISO (BIT(28))
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#define SPI_USR_MOSI (BIT(27))
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#define SPI_USR_DUMMY_IDLE (BIT(26))
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#define SPI_USR_MOSI_HIGHPART (BIT(25))
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#define SPI_USR_MISO_HIGHPART (BIT(24))
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#define SPI_USR_PREP_HOLD (BIT(23))
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#define SPI_USR_CMD_HOLD (BIT(22))
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#define SPI_USR_ADDR_HOLD (BIT(21))
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#define SPI_USR_DUMMY_HOLD (BIT(20))
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#define SPI_USR_DIN_HOLD (BIT(19))
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#define SPI_USR_DOUT_HOLD (BIT(18))
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#define SPI_USR_HOLD_POL (BIT(17))
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#define SPI_SIO (BIT(16))
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#define SPI_FWRITE_QIO (BIT(15))
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#define SPI_FWRITE_DIO (BIT(14))
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#define SPI_FWRITE_QUAD (BIT(13))
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#define SPI_FWRITE_DUAL (BIT(12))
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#define SPI_WR_BYTE_ORDER (BIT(11))
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#define SPI_RD_BYTE_ORDER (BIT(10))
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#define SPI_CK_OUT_EDGE (BIT(7))
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#define SPI_CK_I_EDGE (BIT(6))
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#define SPI_CS_SETUP (BIT(5))
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#define SPI_CS_HOLD (BIT(4))
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#define SPI_DOUTDIN (BIT(0))
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#define SPI_USER1( i ) (REG_SPI_BASE( i ) + 0x20)
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#define SPI_USR_ADDR_BITLEN 0x0000003F
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#define SPI_USR_ADDR_BITLEN_S 26
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#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
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#define SPI_USR_DUMMY_CYCLELEN_S 0
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#define SPI_USER2( i ) (REG_SPI_BASE( i ) + 0x24)
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#define SPI_USR_COMMAND_BITLEN 0x0000000F
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#define SPI_USR_COMMAND_BITLEN_S 28
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#define SPI_USR_COMMAND_VALUE 0x0000FFFF
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#define SPI_USR_COMMAND_VALUE_S 0
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#define SPI_MOSI_DLEN( i ) (REG_SPI_BASE( i ) + 0x28)
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#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF
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#define SPI_USR_MOSI_DBITLEN_S 0
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#define SPI_MISO_DLEN( i ) (REG_SPI_BASE( i ) + 0x2C)
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#define SPI_USR_MISO_DBITLEN 0x00FFFFFF
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#define SPI_USR_MISO_DBITLEN_S 0
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#define SPI_SLV_WR_STATUS( i ) (REG_SPI_BASE( i ) + 0x30)
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#define SPI_PIN( i ) (REG_SPI_BASE( i ) + 0x34)
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#define SPI_CS_KEEP_ACTIVE (BIT(30))
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#define SPI_CK_IDLE_EDGE (BIT(29))
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#define SPI_CSCK_SEL (BIT(19))
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#define SPI_MASTER_CK_SEL 0x0000001F
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#define SPI_MASTER_CK_SEL_S 11
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#define SPI_MASTER_CS_POL 0x0000001F
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#define SPI_MASTER_CS_POL_S 6
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#define SPI_CK_DIS (BIT(5))
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#define SPI_CS2_DIS (BIT(2))
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#define SPI_CS1_DIS (BIT(1))
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#define SPI_CS0_DIS (BIT(0))
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#define SPI_SLAVE( i ) (REG_SPI_BASE( i ) + 0x38)
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#define SPI_SYNC_RESET (BIT(31))
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#define SPI_SLAVE_MODE (BIT(30))
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#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
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#define SPI_SLV_WR_RD_STA_EN (BIT(28))
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#define SPI_SLV_CMD_DEFINE (BIT(27))
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#define SPI_TRANS_CNT 0x0000000F
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#define SPI_TRANS_CNT_S 23
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#define SPI_SLV_LAST_STATE 0x00000007
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#define SPI_SLV_LAST_STATE_S 20
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#define SPI_SLV_LAST_COMMAND 0x00000007
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#define SPI_SLV_LAST_COMMAND_S 17
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#define SPI_CS_I_MODE 0x00000003
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#define SPI_CS_I_MODE_S 10
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#define SPI_INT_EN 0x0000001F
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#define SPI_INT_EN_S 5
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#define SPI_TRANS_DONE (BIT(4))
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#define SPI_SLV_WR_STA_DONE (BIT(3))
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#define SPI_SLV_RD_STA_DONE (BIT(2))
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#define SPI_SLV_WR_BUF_DONE (BIT(1))
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#define SPI_SLV_RD_BUF_DONE (BIT(0))
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#define SPI_SLAVE1( i ) (REG_SPI_BASE( i ) + 0x3C)
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#define SPI_SLV_STATUS_BITLEN 0x0000001F
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#define SPI_SLV_STATUS_BITLEN_S 27
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#define SPI_SLV_STATUS_FAST_EN (BIT(26))
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#define SPI_SLV_STATUS_READBACK (BIT(25))
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#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
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#define SPI_SLV_RD_ADDR_BITLEN_S 10
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#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
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#define SPI_SLV_WR_ADDR_BITLEN_S 4
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#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
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#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
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#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
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#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
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#define SPI_SLAVE2( i ) (REG_SPI_BASE( i ) + 0x40)
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#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF
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#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
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#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF
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#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
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#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF
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#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8
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#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF
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#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0
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#define SPI_SLAVE3( i ) (REG_SPI_BASE( i ) + 0x44)
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#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
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#define SPI_SLV_WRSTA_CMD_VALUE_S 24
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#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
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#define SPI_SLV_RDSTA_CMD_VALUE_S 16
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#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
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#define SPI_SLV_WRBUF_CMD_VALUE_S 8
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#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
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#define SPI_SLV_RDBUF_CMD_VALUE_S 0
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#define SPI_SLV_WRBUF_DLEN( i ) (REG_SPI_BASE( i ) + 0x48)
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#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF
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#define SPI_SLV_WRBUF_DBITLEN_S 0
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#define SPI_SLV_RDBUF_DLEN( i ) (REG_SPI_BASE( i ) + 0x4C)
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#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF
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#define SPI_SLV_RDBUF_DBITLEN_S 0
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#define SPI_CACHE_FCTRL( i ) (REG_SPI_BASE( i ) + 0x50)
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#define SPI_CACHE_FLASH_PES_EN (BIT(3))
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#define SPI_CACHE_FLASH_USR_CMD (BIT(2))
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#define SPI_CACHE_USR_CMD_4BYTE (BIT(1))
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#define SPI_CACHE_REQ_EN (BIT(0))
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#define SPI_CACHE_SCTRL( i ) (REG_SPI_BASE( i ) + 0x54)
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#define SPI_CACHE_SRAM_USR_WCMD (BIT(28))
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#define SPI_SRAM_ADDR_BITLEN 0x0000003F
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#define SPI_SRAM_ADDR_BITLEN_S 22
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#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF
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#define SPI_SRAM_DUMMY_CYCLELEN_S 14
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#define SPI_SRAM_BYTES_LEN 0x000000FF
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#define SPI_SRAM_BYTES_LEN_S 6
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#define SPI_CACHE_SRAM_USR_RCMD (BIT(5))
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#define SPI_USR_RD_SRAM_DUMMY (BIT(4))
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#define SPI_USR_WR_SRAM_DUMMY (BIT(3))
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#define SPI_USR_SRAM_QIO (BIT(2))
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#define SPI_USR_SRAM_DIO (BIT(1))
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#define SPI_SRAM_CMD( i ) (REG_SPI_BASE( i ) + 0x58)
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#define SPI_SRAM_RSTIO (BIT(4))
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#define SPI_SRAM_QIO (BIT(1))
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#define SPI_SRAM_DIO (BIT(0))
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#define SPI_SRAM_DRD_CMD( i ) (REG_SPI_BASE( i ) + 0x5C)
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#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F
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#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28
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#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF
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#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0
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#define SPI_SRAM_DWR_CMD( i ) (REG_SPI_BASE( i ) + 0x60)
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#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F
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#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28
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#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF
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#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0
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#define SPI_SLV_RD_BIT( i ) (REG_SPI_BASE( i ) + 0x64)
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#define SPI_SLV_RDATA_BIT 0x00FFFFFF
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#define SPI_SLV_RDATA_BIT_S 0
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#define SPI_W0( i ) (REG_SPI_BASE( i ) + 0x80)
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#define SPI_W1( i ) (REG_SPI_BASE( i ) + 0x84)
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#define SPI_W2( i ) (REG_SPI_BASE( i ) + 0x88)
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#define SPI_W3( i ) (REG_SPI_BASE( i ) + 0x8C)
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#define SPI_W4( i ) (REG_SPI_BASE( i ) + 0x90)
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#define SPI_W5( i ) (REG_SPI_BASE( i ) + 0x94)
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#define SPI_W6( i ) (REG_SPI_BASE( i ) + 0x98)
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#define SPI_W7( i ) (REG_SPI_BASE( i ) + 0x9C)
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#define SPI_W8( i ) (REG_SPI_BASE( i ) + 0xA0)
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#define SPI_W9( i ) (REG_SPI_BASE( i ) + 0xA4)
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#define SPI_W10( i ) (REG_SPI_BASE( i ) + 0xA8)
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#define SPI_W11( i ) (REG_SPI_BASE( i ) + 0xAC)
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#define SPI_W12( i ) (REG_SPI_BASE( i ) + 0xB0)
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#define SPI_W13( i ) (REG_SPI_BASE( i ) + 0xB4)
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#define SPI_W14( i ) (REG_SPI_BASE( i ) + 0xB8)
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#define SPI_W15( i ) (REG_SPI_BASE( i ) + 0xBC)
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#define SPI_TX_CRC( i ) (REG_SPI_BASE( i ) + 0xC0)
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#define SPI_EXT0( i ) (REG_SPI_BASE( i ) + 0xF0)
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#define SPI_T_PP_ENA (BIT(31))
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#define SPI_T_PP_SHIFT 0x0000000F
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#define SPI_T_PP_SHIFT_S 16
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#define SPI_T_PP_TIME 0x00000FFF
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#define SPI_T_PP_TIME_S 0
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#define SPI_EXT1( i ) (REG_SPI_BASE( i ) + 0xF4)
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#define SPI_T_ERASE_ENA (BIT(31))
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#define SPI_T_ERASE_SHIFT 0x0000000F
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#define SPI_T_ERASE_SHIFT_S 16
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#define SPI_T_ERASE_TIME 0x00000FFF
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#define SPI_T_ERASE_TIME_S 0
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#define SPI_EXT2( i ) (REG_SPI_BASE( i ) + 0xF8)
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#define SPI_ST 0x00000007
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#define SPI_ST_S 0
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#define SPI_EXT3( i ) (REG_SPI_BASE( i ) + 0xFC)
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#define SPI_INT_HOLD_ENA 0x00000003
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#define SPI_INT_HOLD_ENA_S 0
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#define SPI_DMA_CONF( i ) (REG_SPI_BASE( i ) + 0x100)
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#define SPI_DMA_CONTINUE (BIT(16))
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#define SPI_DMA_TX_STOP (BIT(15))
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#define SPI_DMA_RX_STOP (BIT(14))
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#define SPI_OUT_DATA_BURST_EN (BIT(12))
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#define SPI_INDSCR_BURST_EN (BIT(11))
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#define SPI_OUTDSCR_BURST_EN (BIT(10))
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#define SPI_OUT_EOF_MODE (BIT(9))
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#define SPI_OUT_AUTO_WRBACK (BIT(8))
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#define SPI_OUT_LOOP_TEST (BIT(7))
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#define SPI_IN_LOOP_TEST (BIT(6))
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#define SPI_AHBM_RST (BIT(5))
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#define SPI_AHBM_FIFO_RST (BIT(4))
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#define SPI_OUT_RST (BIT(3))
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#define SPI_IN_RST (BIT(2))
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#define SPI_DMA_OUT_LINK( i ) (REG_SPI_BASE( i ) + 0x104)
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#define SPI_OUTLINK_RESTART (BIT(30))
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#define SPI_OUTLINK_START (BIT(29))
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#define SPI_OUTLINK_STOP (BIT(28))
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#define SPI_OUTLINK_ADDR 0x000FFFFF
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#define SPI_OUTLINK_ADDR_S 0
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#define SPI_DMA_IN_LINK( i ) (REG_SPI_BASE( i ) + 0x108)
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#define SPI_INLINK_RESTART (BIT(30))
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#define SPI_INLINK_START (BIT(29))
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#define SPI_INLINK_STOP (BIT(28))
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#define SPI_INLINK_AUTO_RET (BIT(20))
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#define SPI_INLINK_ADDR 0x000FFFFF
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#define SPI_INLINK_ADDR_S 0
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#define SPI_DMA_STATUS( i ) (REG_SPI_BASE( i ) + 0x10C)
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#define SPI_DMA_TX_EN (BIT(1))
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#define SPI_DMA_RX_EN (BIT(0))
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#define SPI_DMA_INT_ENA( i ) (REG_SPI_BASE( i ) + 0x110)
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#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8))
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#define SPI_OUT_EOF_INT_ENA (BIT(7))
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#define SPI_OUT_DONE_INT_ENA (BIT(6))
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#define SPI_IN_SUC_EOF_INT_ENA (BIT(5))
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#define SPI_IN_ERR_EOF_INT_ENA (BIT(4))
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#define SPI_IN_DONE_INT_ENA (BIT(3))
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#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2))
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#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1))
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#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0))
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#define SPI_DMA_INT_RAW( i ) (REG_SPI_BASE( i ) + 0x114)
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#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8))
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#define SPI_OUT_EOF_INT_RAW (BIT(7))
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#define SPI_OUT_DONE_INT_RAW (BIT(6))
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#define SPI_IN_SUC_EOF_INT_RAW (BIT(5))
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#define SPI_IN_ERR_EOF_INT_RAW (BIT(4))
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#define SPI_IN_DONE_INT_RAW (BIT(3))
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#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2))
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#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1))
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#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0))
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#define SPI_DMA_INT_ST( i ) (REG_SPI_BASE( i ) + 0x118)
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#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8))
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#define SPI_OUT_EOF_INT_ST (BIT(7))
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#define SPI_OUT_DONE_INT_ST (BIT(6))
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#define SPI_IN_SUC_EOF_INT_ST (BIT(5))
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#define SPI_IN_ERR_EOF_INT_ST (BIT(4))
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#define SPI_IN_DONE_INT_ST (BIT(3))
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#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2))
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#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1))
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#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0))
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#define SPI_DMA_INT_CLR( i ) (REG_SPI_BASE( i ) + 0x11C)
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#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8))
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#define SPI_OUT_EOF_INT_CLR (BIT(7))
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#define SPI_OUT_DONE_INT_CLR (BIT(6))
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#define SPI_IN_SUC_EOF_INT_CLR (BIT(5))
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#define SPI_IN_ERR_EOF_INT_CLR (BIT(4))
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#define SPI_IN_DONE_INT_CLR (BIT(3))
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#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2))
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#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1))
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#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0))
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#define SPI_IN_ERR_EOF_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x120)
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#define SPI_IN_SUC_EOF_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x124)
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#define SPI_INLINK_DSCR( i ) (REG_SPI_BASE( i ) + 0x128)
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#define SPI_INLINK_DSCR_BF0( i ) (REG_SPI_BASE( i ) + 0x12C)
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#define SPI_INLINK_DSCR_BF1( i ) (REG_SPI_BASE( i ) + 0x130)
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#define SPI_OUT_EOF_BFR_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x134)
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#define SPI_OUT_EOF_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x138)
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#define SPI_OUTLINK_DSCR( i ) (REG_SPI_BASE( i ) + 0x13C)
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#define SPI_OUTLINK_DSCR_BF0( i ) (REG_SPI_BASE( i ) + 0x140)
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||
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#define SPI_OUTLINK_DSCR_BF1( i ) (REG_SPI_BASE( i ) + 0x144)
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||
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#define SPI_DMA_RSTATUS( i ) (REG_SPI_BASE( i ) + 0x148)
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||
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#define SPI_DMA_TSTATUS( i ) (REG_SPI_BASE( i ) + 0x14C)
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||
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#define SPI_REG_DATE( i ) (REG_SPI_BASE( i ) + 0x3FC)
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||
|
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#define SPI_DATE 0x0FFFFFFF
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||
|
|
#define SPI_DATE_S 0
|
||
|
|
#define SPI_DATE_VERSION 0x1604290
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||
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#endif /* _SOC_SPI_REG_H_ */
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