752 lines
28 KiB
C
752 lines
28 KiB
C
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_RTC_CNTL_REG_H_
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#define _SOC_RTC_CNTL_REG_H_
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#include "soc.h"
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#define RTC_OPTIONS0 (DR_REG_RTCCNTL_BASE + 0x0)
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#define RTC_CNTL_SW_SYS_RST (BIT(31))
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#define RTC_CNTL_SW_SYS_RST_S 31
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#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30))
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#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30
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#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))
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#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29
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#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))
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#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28
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#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27))
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#define RTC_CNTL_PLL_FORCE_NOISO_S 27
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#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26))
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#define RTC_CNTL_XTL_FORCE_NOISO_S 26
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#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25))
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#define RTC_CNTL_ANALOG_FORCE_ISO_S 25
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#define RTC_CNTL_PLL_FORCE_ISO (BIT(24))
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#define RTC_CNTL_PLL_FORCE_ISO_S 24
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#define RTC_CNTL_XTL_FORCE_ISO (BIT(23))
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#define RTC_CNTL_XTL_FORCE_ISO_S 23
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#define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22))
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#define RTC_CNTL_BIAS_CORE_FORCE_PU_S 22
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#define RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21))
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#define RTC_CNTL_BIAS_CORE_FORCE_PD_S 21
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#define RTC_CNTL_BIAS_CORE_FOLW_12M (BIT(20))
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#define RTC_CNTL_BIAS_CORE_FOLW_12M_S 20
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#define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19))
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#define RTC_CNTL_BIAS_I2C_FORCE_PU_S 19
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#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18))
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#define RTC_CNTL_BIAS_I2C_FORCE_PD_S 18
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#define RTC_CNTL_BIAS_I2C_FOLW_12M (BIT(17))
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#define RTC_CNTL_BIAS_I2C_FOLW_12M_S 17
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#define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16))
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#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16
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#define RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15))
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#define RTC_CNTL_BIAS_FORCE_SLEEP_S 15
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#define RTC_CNTL_BIAS_SLEEP_FOLW_12M (BIT(14))
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#define RTC_CNTL_BIAS_SLEEP_FOLW_12M_S 14
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#define RTC_CNTL_XTL_FORCE_PU (BIT(13))
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#define RTC_CNTL_XTL_FORCE_PU_S 13
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#define RTC_CNTL_XTL_FORCE_PD (BIT(12))
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#define RTC_CNTL_XTL_FORCE_PD_S 12
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#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11))
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#define RTC_CNTL_BBPLL_FORCE_PU_S 11
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#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10))
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#define RTC_CNTL_BBPLL_FORCE_PD_S 10
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#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9))
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#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9
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#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8))
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#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8
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#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7))
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#define RTC_CNTL_BB_I2C_FORCE_PU_S 7
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#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6))
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#define RTC_CNTL_BB_I2C_FORCE_PD_S 6
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#define RTC_CNTL_SW_PROCPU_RST (BIT(5))
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#define RTC_CNTL_SW_PROCPU_RST_S 5
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#define RTC_CNTL_SW_APPCPU_RST (BIT(4))
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#define RTC_CNTL_SW_APPCPU_RST_S 4
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#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003
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#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2
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#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003
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#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0
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#define RTC_SLP_TIMER0 (DR_REG_RTCCNTL_BASE + 0x4)
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#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF
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#define RTC_CNTL_SLP_VAL_LO_S 0
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#define RTC_SLP_TIMER1 (DR_REG_RTCCNTL_BASE + 0x8)
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#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN (BIT(16))
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#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_S 16
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#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF
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#define RTC_CNTL_SLP_VAL_HI_S 0
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#define RTC_TIME_UPDATE (DR_REG_RTCCNTL_BASE + 0xc)
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#define RTC_CNTL_RTC_TIME_UPDATE (BIT(31))
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#define RTC_CNTL_RTC_TIME_UPDATE_S 31
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#define RTC_CNTL_RTC_TIME_VALID (BIT(30))
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#define RTC_CNTL_RTC_TIME_VALID_S 30
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#define RTC_TIME0 (DR_REG_RTCCNTL_BASE + 0x10)
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#define RTC_CNTL_RTC_TIME_LO 0xFFFFFFFF
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#define RTC_CNTL_RTC_TIME_LO_S 0
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#define RTC_TIME1 (DR_REG_RTCCNTL_BASE + 0x14)
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#define RTC_CNTL_RTC_TIME_HI 0x0000FFFF
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#define RTC_CNTL_RTC_TIME_HI_S 0
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#define RTC_STATE0 (DR_REG_RTCCNTL_BASE + 0x18)
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#define RTC_CNTL_SLEEP_EN (BIT(31))
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#define RTC_CNTL_SLEEP_EN_S 31
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#define RTC_CNTL_SLP_REJECT (BIT(30))
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#define RTC_CNTL_SLP_REJECT_S 30
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#define RTC_CNTL_SLP_WAKEUP (BIT(29))
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#define RTC_CNTL_SLP_WAKEUP_S 29
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#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28))
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#define RTC_CNTL_SDIO_ACTIVE_IND_S 28
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#define RTC_CNTL_SAR_SLP_TIMER_EN (BIT(24))
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#define RTC_CNTL_SAR_SLP_TIMER_EN_S 24
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#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(23))
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#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 23
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#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22))
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#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22
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#define RTC_CNTL_SAR_WAKEUP_FORCE_EN (BIT(21))
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#define RTC_CNTL_SAR_WAKEUP_FORCE_EN_S 21
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#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN (BIT(20))
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#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S 20
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#define RTC_TIMER1 (DR_REG_RTCCNTL_BASE + 0x1c)
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#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF
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#define RTC_CNTL_PLL_BUF_WAIT_S 24
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#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF
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#define RTC_CNTL_XTL_BUF_WAIT_S 14
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#define RTC_CNTL_CK12M_WAIT 0x000000FF
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#define RTC_CNTL_CK12M_WAIT_S 6
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#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F
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#define RTC_CNTL_CPU_STALL_WAIT_S 1
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#define RTC_CNTL_CPU_STALL_EN (BIT(0))
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#define RTC_CNTL_CPU_STALL_EN_S 0
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#define RTC_TIMER2 (DR_REG_RTCCNTL_BASE + 0x20)
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#define RTC_CNTL_MIN_TIME_CK12M_OFF 0x000000FF
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#define RTC_CNTL_MIN_TIME_CK12M_OFF_S 24
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#define RTC_CNTL_SAR_TOUCH_START_WAIT 0x000001FF
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#define RTC_CNTL_SAR_TOUCH_START_WAIT_S 15
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#define RTC_TIMER3 (DR_REG_RTCCNTL_BASE + 0x24)
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#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F
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#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25
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#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF
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#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16
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#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F
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#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9
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#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF
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#define RTC_CNTL_WIFI_WAIT_TIMER_S 0
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#define RTC_TIMER4 (DR_REG_RTCCNTL_BASE + 0x28)
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#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F
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#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25
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#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF
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#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16
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#define RTC_CNTL_RTC_POWERUP_TIMER 0x0000007F
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#define RTC_CNTL_RTC_POWERUP_TIMER_S 9
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#define RTC_CNTL_RTC_WAIT_TIMER 0x000001FF
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#define RTC_CNTL_RTC_WAIT_TIMER_S 0
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#define RTC_TIMER5 (DR_REG_RTCCNTL_BASE + 0x2c)
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#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F
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#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25
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#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF
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#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16
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#define RTC_CNTL_MIN_SLP_VAL 0x000000FF
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#define RTC_CNTL_MIN_SLP_VAL_S 8
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#define RTC_CNTL_SAR_SUBTIMER_PREDIV 0x000000FF
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#define RTC_CNTL_SAR_SUBTIMER_PREDIV_S 0
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#define RTC_ANA_CONF (DR_REG_RTCCNTL_BASE + 0x30)
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#define RTC_CNTL_PLL_I2C_PU (BIT(31))
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#define RTC_CNTL_PLL_I2C_PU_S 31
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#define RTC_CNTL_CKGEN_I2C_PU (BIT(30))
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#define RTC_CNTL_CKGEN_I2C_PU_S 30
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#define RTC_CNTL_RFRX_PBUS_PU (BIT(28))
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#define RTC_CNTL_RFRX_PBUS_PU_S 28
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#define RTC_CNTL_TXRF_I2C_PU (BIT(27))
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#define RTC_CNTL_TXRF_I2C_PU_S 27
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#define RTC_CNTL_PVTMON_PU (BIT(26))
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#define RTC_CNTL_PVTMON_PU_S 26
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#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25))
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#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25
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#define RTC_CNTL_PLLA_FORCE_PU (BIT(24))
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#define RTC_CNTL_PLLA_FORCE_PU_S 24
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#define RTC_CNTL_PLLA_FORCE_PD (BIT(23))
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#define RTC_CNTL_PLLA_FORCE_PD_S 23
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#define RTC_RESET_STATE (DR_REG_RTCCNTL_BASE + 0x34)
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#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13))
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#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13
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#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12))
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#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12
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#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F
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#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6
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#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F
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#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0
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#define RTC_WAKEUP_STATE (DR_REG_RTCCNTL_BASE + 0x38)
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#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22))
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#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22
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#define RTC_CNTL_RTC_WAKEUP_ENA 0x000007FF
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#define RTC_CNTL_RTC_WAKEUP_ENA_S 11
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#define RTC_CNTL_WAKEUP_CAUSE 0x000007FF
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#define RTC_CNTL_WAKEUP_CAUSE_S 0
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#define INT_ENA_RTC (DR_REG_RTCCNTL_BASE + 0x3c)
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#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA (BIT(8))
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#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_S 8
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#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA (BIT(7))
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#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_S 7
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#define RTC_CNTL_RTC_TOUCH_INT_ENA (BIT(6))
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#define RTC_CNTL_RTC_TOUCH_INT_ENA_S 6
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#define RTC_CNTL_RTC_SAR_INT_ENA (BIT(5))
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#define RTC_CNTL_RTC_SAR_INT_ENA_S 5
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#define RTC_CNTL_RTC_TIME_VALID_INT_ENA (BIT(4))
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#define RTC_CNTL_RTC_TIME_VALID_INT_ENA_S 4
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#define RTC_CNTL_RTC_WDT_INT_ENA (BIT(3))
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#define RTC_CNTL_RTC_WDT_INT_ENA_S 3
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#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2))
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#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2
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#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1))
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#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1
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#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0))
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#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0
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#define INT_RAW_RTC (DR_REG_RTCCNTL_BASE + 0x40)
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#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW (BIT(8))
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#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_S 8
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#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW (BIT(7))
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#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW_S 7
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#define RTC_CNTL_RTC_TOUCH_INT_RAW (BIT(6))
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#define RTC_CNTL_RTC_TOUCH_INT_RAW_S 6
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#define RTC_CNTL_RTC_SAR_INT_RAW (BIT(5))
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#define RTC_CNTL_RTC_SAR_INT_RAW_S 5
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#define RTC_CNTL_RTC_TIME_VALID_INT_RAW (BIT(4))
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#define RTC_CNTL_RTC_TIME_VALID_INT_RAW_S 4
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#define RTC_CNTL_RTC_WDT_INT_RAW (BIT(3))
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#define RTC_CNTL_RTC_WDT_INT_RAW_S 3
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#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2))
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#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2
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#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1))
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#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1
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#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0))
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#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0
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#define INT_ST_RTC (DR_REG_RTCCNTL_BASE + 0x44)
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#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST (BIT(8))
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#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST_S 8
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#define RTC_CNTL_RTC_BROWN_OUT_INT_ST (BIT(7))
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#define RTC_CNTL_RTC_BROWN_OUT_INT_ST_S 7
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#define RTC_CNTL_RTC_TOUCH_INT_ST (BIT(6))
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#define RTC_CNTL_RTC_TOUCH_INT_ST_S 6
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#define RTC_CNTL_RTC_SAR_INT_ST (BIT(5))
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#define RTC_CNTL_RTC_SAR_INT_ST_S 5
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#define RTC_CNTL_RTC_TIME_VALID_INT_ST (BIT(4))
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#define RTC_CNTL_RTC_TIME_VALID_INT_ST_S 4
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|
|
#define RTC_CNTL_RTC_WDT_INT_ST (BIT(3))
|
||
|
|
#define RTC_CNTL_RTC_WDT_INT_ST_S 3
|
||
|
|
#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2))
|
||
|
|
#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2
|
||
|
|
#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1))
|
||
|
|
#define RTC_CNTL_SLP_REJECT_INT_ST_S 1
|
||
|
|
#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0))
|
||
|
|
#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0
|
||
|
|
|
||
|
|
#define INT_CLR_RTC (DR_REG_RTCCNTL_BASE + 0x48)
|
||
|
|
#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR (BIT(8))
|
||
|
|
#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_S 8
|
||
|
|
#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR (BIT(7))
|
||
|
|
#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR_S 7
|
||
|
|
#define RTC_CNTL_RTC_TOUCH_INT_CLR (BIT(6))
|
||
|
|
#define RTC_CNTL_RTC_TOUCH_INT_CLR_S 6
|
||
|
|
#define RTC_CNTL_RTC_SAR_INT_CLR (BIT(5))
|
||
|
|
#define RTC_CNTL_RTC_SAR_INT_CLR_S 5
|
||
|
|
#define RTC_CNTL_RTC_TIME_VALID_INT_CLR (BIT(4))
|
||
|
|
#define RTC_CNTL_RTC_TIME_VALID_INT_CLR_S 4
|
||
|
|
#define RTC_CNTL_RTC_WDT_INT_CLR (BIT(3))
|
||
|
|
#define RTC_CNTL_RTC_WDT_INT_CLR_S 3
|
||
|
|
#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2))
|
||
|
|
#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2
|
||
|
|
#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1))
|
||
|
|
#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1
|
||
|
|
#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0))
|
||
|
|
#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0
|
||
|
|
|
||
|
|
#define RTC_STORE0 (DR_REG_RTCCNTL_BASE + 0x4c)
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH0 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH0_S 0
|
||
|
|
|
||
|
|
#define RTC_STORE1 (DR_REG_RTCCNTL_BASE + 0x50)
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH1 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH1_S 0
|
||
|
|
|
||
|
|
#define RTC_STORE2 (DR_REG_RTCCNTL_BASE + 0x54)
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH2 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH2_S 0
|
||
|
|
|
||
|
|
#define RTC_STORE3 (DR_REG_RTCCNTL_BASE + 0x58)
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH3 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH3_S 0
|
||
|
|
|
||
|
|
#define RTC_EXT_XTL_CONF (DR_REG_RTCCNTL_BASE + 0x5c)
|
||
|
|
#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31))
|
||
|
|
#define RTC_CNTL_XTL_EXT_CTR_EN_S 31
|
||
|
|
#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30))
|
||
|
|
#define RTC_CNTL_XTL_EXT_CTR_LV_S 30
|
||
|
|
|
||
|
|
#define RTC_EXT_WAKEUP_CONF (DR_REG_RTCCNTL_BASE + 0x60)
|
||
|
|
#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31))
|
||
|
|
#define RTC_CNTL_EXT_WAKEUP1_LV_S 31
|
||
|
|
#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30))
|
||
|
|
#define RTC_CNTL_EXT_WAKEUP0_LV_S 30
|
||
|
|
|
||
|
|
#define RTC_SLP_REJECT_CONF (DR_REG_RTCCNTL_BASE + 0x64)
|
||
|
|
#define RTC_CNTL_REJECT_CAUSE 0x0000000F
|
||
|
|
#define RTC_CNTL_REJECT_CAUSE_S 28
|
||
|
|
#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(27))
|
||
|
|
#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 27
|
||
|
|
#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(26))
|
||
|
|
#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 26
|
||
|
|
#define RTC_CNTL_SDIO_REJECT_EN (BIT(25))
|
||
|
|
#define RTC_CNTL_SDIO_REJECT_EN_S 25
|
||
|
|
#define RTC_CNTL_GPIO_REJECT_EN (BIT(24))
|
||
|
|
#define RTC_CNTL_GPIO_REJECT_EN_S 24
|
||
|
|
|
||
|
|
#define RTC_CPU_PERIOD_CONF (DR_REG_RTCCNTL_BASE + 0x68)
|
||
|
|
#define RTC_CNTL_RTC_CPUPERIOD_SEL 0x00000003
|
||
|
|
#define RTC_CNTL_RTC_CPUPERIOD_SEL_S 30
|
||
|
|
#define RTC_CNTL_RTC_CPUSEL_CONF (BIT(29))
|
||
|
|
#define RTC_CNTL_RTC_CPUSEL_CONF_S 29
|
||
|
|
|
||
|
|
#define RTC_SDIO_ACT_CONF (DR_REG_RTCCNTL_BASE + 0x6c)
|
||
|
|
#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF
|
||
|
|
#define RTC_CNTL_SDIO_ACT_DNUM_S 22
|
||
|
|
|
||
|
|
#define RTC_CLK_CONF (DR_REG_RTCCNTL_BASE + 0x70)
|
||
|
|
#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003
|
||
|
|
#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30
|
||
|
|
#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29))
|
||
|
|
#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29
|
||
|
|
#define RTC_CNTL_SOC_CLK_SEL 0x00000003
|
||
|
|
#define RTC_CNTL_SOC_CLK_SEL_S 27
|
||
|
|
#define RTC_CNTL_CK12M_FORCE_PU (BIT(26))
|
||
|
|
#define RTC_CNTL_CK12M_FORCE_PU_S 26
|
||
|
|
#define RTC_CNTL_CK12M_FORCE_PD (BIT(25))
|
||
|
|
#define RTC_CNTL_CK12M_FORCE_PD_S 25
|
||
|
|
#define RTC_CNTL_CK12M_DFREQ 0x000000FF
|
||
|
|
#define RTC_CNTL_CK12M_DFREQ_S 17
|
||
|
|
#define RTC_CNTL_CK12M_FORCE_NOGATING (BIT(16))
|
||
|
|
#define RTC_CNTL_CK12M_FORCE_NOGATING_S 16
|
||
|
|
#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15))
|
||
|
|
#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15
|
||
|
|
#define RTC_CNTL_CK12M_DIV_SEL 0x00000007
|
||
|
|
#define RTC_CNTL_CK12M_DIV_SEL_S 12
|
||
|
|
#define RTC_CNTL_CK12M_DFREQ_FORCE (BIT(11))
|
||
|
|
#define RTC_CNTL_CK12M_DFREQ_FORCE_S 11
|
||
|
|
#define RTC_CNTL_DIG_CLK12M_EN (BIT(10))
|
||
|
|
#define RTC_CNTL_DIG_CLK12M_EN_S 10
|
||
|
|
#define RTC_CNTL_DIG_CLK12M_D256_EN (BIT(9))
|
||
|
|
#define RTC_CNTL_DIG_CLK12M_D256_EN_S 9
|
||
|
|
#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8))
|
||
|
|
#define RTC_CNTL_DIG_XTAL32K_EN_S 8
|
||
|
|
#define RTC_CNTL_ENB_CK12M_DIV (BIT(7))
|
||
|
|
#define RTC_CNTL_ENB_CK12M_DIV_S 7
|
||
|
|
#define RTC_CNTL_ENB_CK12M (BIT(6))
|
||
|
|
#define RTC_CNTL_ENB_CK12M_S 6
|
||
|
|
#define RTC_CNTL_CK12M_DIV 0x00000003
|
||
|
|
#define RTC_CNTL_CK12M_DIV_S 4
|
||
|
|
|
||
|
|
#define RTC_SDIO_CONF (DR_REG_RTCCNTL_BASE + 0x74)
|
||
|
|
#define RTC_CNTL_XPD_SDIO_REG (BIT(31))
|
||
|
|
#define RTC_CNTL_XPD_SDIO_REG_S 31
|
||
|
|
#define RTC_CNTL_DREFH_SDIO 0x00000003
|
||
|
|
#define RTC_CNTL_DREFH_SDIO_S 29
|
||
|
|
#define RTC_CNTL_DREFM_SDIO 0x00000003
|
||
|
|
#define RTC_CNTL_DREFM_SDIO_S 27
|
||
|
|
#define RTC_CNTL_DREFL_SDIO 0x00000003
|
||
|
|
#define RTC_CNTL_DREFL_SDIO_S 25
|
||
|
|
#define RTC_CNTL_REG1P8_READY (BIT(24))
|
||
|
|
#define RTC_CNTL_REG1P8_READY_S 24
|
||
|
|
#define RTC_CNTL_SDIO_TIEH (BIT(23))
|
||
|
|
#define RTC_CNTL_SDIO_TIEH_S 23
|
||
|
|
#define RTC_CNTL_SDIO_FORCE (BIT(22))
|
||
|
|
#define RTC_CNTL_SDIO_FORCE_S 22
|
||
|
|
#define RTC_CNTL_SDIO_REG_PD_EN (BIT(21))
|
||
|
|
#define RTC_CNTL_SDIO_REG_PD_EN_S 21
|
||
|
|
|
||
|
|
#define RTC_BIAS_CONF (DR_REG_RTCCNTL_BASE + 0x78)
|
||
|
|
#define RTC_CNTL_RST_BIAS_I2C (BIT(31))
|
||
|
|
#define RTC_CNTL_RST_BIAS_I2C_S 31
|
||
|
|
#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30))
|
||
|
|
#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30
|
||
|
|
#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29))
|
||
|
|
#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29
|
||
|
|
#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28))
|
||
|
|
#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28
|
||
|
|
#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27))
|
||
|
|
#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27
|
||
|
|
#define RTC_CNTL_ENB_SCK_XTAL (BIT(26))
|
||
|
|
#define RTC_CNTL_ENB_SCK_XTAL_S 26
|
||
|
|
#define RTC_CNTL_DBG_ATTEN 0x00000003
|
||
|
|
#define RTC_CNTL_DBG_ATTEN_S 24
|
||
|
|
|
||
|
|
#define RTC_REG (DR_REG_RTCCNTL_BASE + 0x7c)
|
||
|
|
#define RTC_CNTL_RTC_REG_FORCE_PU (BIT(31))
|
||
|
|
#define RTC_CNTL_RTC_REG_FORCE_PU_S 31
|
||
|
|
#define RTC_CNTL_RTC_REG_FORCE_PD (BIT(30))
|
||
|
|
#define RTC_CNTL_RTC_REG_FORCE_PD_S 30
|
||
|
|
#define RTC_CNTL_RTC_DBOOST_FORCE_PU (BIT(29))
|
||
|
|
#define RTC_CNTL_RTC_DBOOST_FORCE_PU_S 29
|
||
|
|
#define RTC_CNTL_RTC_DBOOST_FORCE_PD (BIT(28))
|
||
|
|
#define RTC_CNTL_RTC_DBOOST_FORCE_PD_S 28
|
||
|
|
#define RTC_CNTL_RTC_DBIAS_WAK 0x00000007
|
||
|
|
#define RTC_CNTL_RTC_DBIAS_WAK_S 25
|
||
|
|
#define RTC_CNTL_RTC_DBIAS_SLP 0x00000007
|
||
|
|
#define RTC_CNTL_RTC_DBIAS_SLP_S 22
|
||
|
|
#define RTC_CNTL_SCK_DCAP 0x000000FF
|
||
|
|
#define RTC_CNTL_SCK_DCAP_S 14
|
||
|
|
#define RTC_CNTL_DIG_REG_DBIAS_WAK 0x00000007
|
||
|
|
#define RTC_CNTL_DIG_REG_DBIAS_WAK_S 11
|
||
|
|
#define RTC_CNTL_DIG_REG_DBIAS_SLP 0x00000007
|
||
|
|
#define RTC_CNTL_DIG_REG_DBIAS_SLP_S 8
|
||
|
|
#define RTC_CNTL_SCK_DCAP_FORCE (BIT(7))
|
||
|
|
#define RTC_CNTL_SCK_DCAP_FORCE_S 7
|
||
|
|
|
||
|
|
#define RTC_PWC (DR_REG_RTCCNTL_BASE + 0x80)
|
||
|
|
#define RTC_CNTL_RTC_PD_EN (BIT(20))
|
||
|
|
#define RTC_CNTL_RTC_PD_EN_S 20
|
||
|
|
#define RTC_CNTL_RTC_FORCE_PU (BIT(19))
|
||
|
|
#define RTC_CNTL_RTC_FORCE_PU_S 19
|
||
|
|
#define RTC_CNTL_RTC_FORCE_PD (BIT(18))
|
||
|
|
#define RTC_CNTL_RTC_FORCE_PD_S 18
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_PD_EN (BIT(17))
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_PD_EN_S 17
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FORCE_PU (BIT(16))
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FORCE_PU_S 16
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FORCE_PD (BIT(15))
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FORCE_PD_S 15
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_PD_EN (BIT(14))
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_PD_EN_S 14
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FORCE_PU (BIT(13))
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FORCE_PU_S 13
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FORCE_PD (BIT(12))
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FORCE_PD_S 12
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU (BIT(11))
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_S 11
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD (BIT(10))
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_S 10
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU (BIT(9))
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_S 9
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU (BIT(8))
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU_S 8
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD (BIT(7))
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD_S 7
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU (BIT(6))
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU_S 6
|
||
|
|
#define RTC_CNTL_RTC_FORCE_NOISO (BIT(5))
|
||
|
|
#define RTC_CNTL_RTC_FORCE_NOISO_S 5
|
||
|
|
#define RTC_CNTL_RTC_FORCE_ISO (BIT(4))
|
||
|
|
#define RTC_CNTL_RTC_FORCE_ISO_S 4
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO (BIT(3))
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_S 3
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO (BIT(2))
|
||
|
|
#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_S 2
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO (BIT(1))
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO_S 1
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO (BIT(0))
|
||
|
|
#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_S 0
|
||
|
|
|
||
|
|
#define DIG_PWC (DR_REG_RTCCNTL_BASE + 0x84)
|
||
|
|
#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31))
|
||
|
|
#define RTC_CNTL_DG_WRAP_PD_EN_S 31
|
||
|
|
#define RTC_CNTL_WIFI_PD_EN (BIT(30))
|
||
|
|
#define RTC_CNTL_WIFI_PD_EN_S 30
|
||
|
|
#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29))
|
||
|
|
#define RTC_CNTL_INTER_RAM4_PD_EN_S 29
|
||
|
|
#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28))
|
||
|
|
#define RTC_CNTL_INTER_RAM3_PD_EN_S 28
|
||
|
|
#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27))
|
||
|
|
#define RTC_CNTL_INTER_RAM2_PD_EN_S 27
|
||
|
|
#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26))
|
||
|
|
#define RTC_CNTL_INTER_RAM1_PD_EN_S 26
|
||
|
|
#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25))
|
||
|
|
#define RTC_CNTL_INTER_RAM0_PD_EN_S 25
|
||
|
|
#define RTC_CNTL_ROM0_PD_EN (BIT(24))
|
||
|
|
#define RTC_CNTL_ROM0_PD_EN_S 24
|
||
|
|
#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20))
|
||
|
|
#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20
|
||
|
|
#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19))
|
||
|
|
#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19
|
||
|
|
#define RTC_CNTL_WIFI_FORCE_PU (BIT(18))
|
||
|
|
#define RTC_CNTL_WIFI_FORCE_PU_S 18
|
||
|
|
#define RTC_CNTL_WIFI_FORCE_PD (BIT(17))
|
||
|
|
#define RTC_CNTL_WIFI_FORCE_PD_S 17
|
||
|
|
#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16))
|
||
|
|
#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16
|
||
|
|
#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15))
|
||
|
|
#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15
|
||
|
|
#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14))
|
||
|
|
#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14
|
||
|
|
#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13))
|
||
|
|
#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13
|
||
|
|
#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12))
|
||
|
|
#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12
|
||
|
|
#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11))
|
||
|
|
#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11
|
||
|
|
#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10))
|
||
|
|
#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10
|
||
|
|
#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9))
|
||
|
|
#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9
|
||
|
|
#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8))
|
||
|
|
#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8
|
||
|
|
#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7))
|
||
|
|
#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7
|
||
|
|
#define RTC_CNTL_ROM0_FORCE_PU (BIT(6))
|
||
|
|
#define RTC_CNTL_ROM0_FORCE_PU_S 6
|
||
|
|
#define RTC_CNTL_ROM0_FORCE_PD (BIT(5))
|
||
|
|
#define RTC_CNTL_ROM0_FORCE_PD_S 5
|
||
|
|
#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4))
|
||
|
|
#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4
|
||
|
|
#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3))
|
||
|
|
#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3
|
||
|
|
|
||
|
|
#define DIG_ISO (DR_REG_RTCCNTL_BASE + 0x88)
|
||
|
|
#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31))
|
||
|
|
#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31
|
||
|
|
#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30))
|
||
|
|
#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30
|
||
|
|
#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29))
|
||
|
|
#define RTC_CNTL_WIFI_FORCE_NOISO_S 29
|
||
|
|
#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28))
|
||
|
|
#define RTC_CNTL_WIFI_FORCE_ISO_S 28
|
||
|
|
#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27))
|
||
|
|
#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27
|
||
|
|
#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26))
|
||
|
|
#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26
|
||
|
|
#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25))
|
||
|
|
#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25
|
||
|
|
#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24))
|
||
|
|
#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24
|
||
|
|
#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23))
|
||
|
|
#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23
|
||
|
|
#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22))
|
||
|
|
#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22
|
||
|
|
#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21))
|
||
|
|
#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21
|
||
|
|
#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20))
|
||
|
|
#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20
|
||
|
|
#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19))
|
||
|
|
#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19
|
||
|
|
#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18))
|
||
|
|
#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18
|
||
|
|
#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17))
|
||
|
|
#define RTC_CNTL_ROM0_FORCE_NOISO_S 17
|
||
|
|
#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16))
|
||
|
|
#define RTC_CNTL_ROM0_FORCE_ISO_S 16
|
||
|
|
#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15))
|
||
|
|
#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15
|
||
|
|
#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14))
|
||
|
|
#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14
|
||
|
|
#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13))
|
||
|
|
#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13
|
||
|
|
#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12))
|
||
|
|
#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12
|
||
|
|
#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11))
|
||
|
|
#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11
|
||
|
|
#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10))
|
||
|
|
#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10
|
||
|
|
#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9))
|
||
|
|
#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9
|
||
|
|
#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8))
|
||
|
|
#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8
|
||
|
|
#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7))
|
||
|
|
#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7
|
||
|
|
|
||
|
|
#define RTC_WDTCONFIG0 (DR_REG_RTCCNTL_BASE + 0x8c)
|
||
|
|
#define RTC_CNTL_WDT_EN (BIT(31))
|
||
|
|
#define RTC_CNTL_WDT_EN_S 31
|
||
|
|
#define RTC_CNTL_WDT_STG0 0x00000007
|
||
|
|
#define RTC_CNTL_WDT_STG0_S 28
|
||
|
|
#define RTC_CNTL_WDT_STG1 0x00000007
|
||
|
|
#define RTC_CNTL_WDT_STG1_S 25
|
||
|
|
#define RTC_CNTL_WDT_STG2 0x00000007
|
||
|
|
#define RTC_CNTL_WDT_STG2_S 22
|
||
|
|
#define RTC_CNTL_WDT_STG3 0x00000007
|
||
|
|
#define RTC_CNTL_WDT_STG3_S 19
|
||
|
|
#define RTC_CNTL_WDT_EDGE_INT_EN (BIT(18))
|
||
|
|
#define RTC_CNTL_WDT_EDGE_INT_EN_S 18
|
||
|
|
#define RTC_CNTL_WDT_LEVEL_INT_EN (BIT(17))
|
||
|
|
#define RTC_CNTL_WDT_LEVEL_INT_EN_S 17
|
||
|
|
#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007
|
||
|
|
#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 14
|
||
|
|
#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007
|
||
|
|
#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 11
|
||
|
|
#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10))
|
||
|
|
#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 10
|
||
|
|
#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(9))
|
||
|
|
#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 9
|
||
|
|
#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(8))
|
||
|
|
#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 8
|
||
|
|
#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7))
|
||
|
|
#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 7
|
||
|
|
|
||
|
|
#define RTC_WDTCONFIG1 (DR_REG_RTCCNTL_BASE + 0x90)
|
||
|
|
#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_WDT_STG0_HOLD_S 0
|
||
|
|
|
||
|
|
#define RTC_WDTCONFIG2 (DR_REG_RTCCNTL_BASE + 0x94)
|
||
|
|
#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_WDT_STG1_HOLD_S 0
|
||
|
|
|
||
|
|
#define RTC_WDTCONFIG3 (DR_REG_RTCCNTL_BASE + 0x98)
|
||
|
|
#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_WDT_STG2_HOLD_S 0
|
||
|
|
|
||
|
|
#define RTC_WDTCONFIG4 (DR_REG_RTCCNTL_BASE + 0x9c)
|
||
|
|
#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_WDT_STG3_HOLD_S 0
|
||
|
|
|
||
|
|
#define RTC_WDTFEED (DR_REG_RTCCNTL_BASE + 0xa0)
|
||
|
|
#define RTC_CNTL_RTC_WDT_FEED (BIT(31))
|
||
|
|
#define RTC_CNTL_RTC_WDT_FEED_S 31
|
||
|
|
|
||
|
|
#define RTC_WDTWPROTECT (DR_REG_RTCCNTL_BASE + 0xa4)
|
||
|
|
#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_WDT_WKEY_S 0
|
||
|
|
|
||
|
|
#define RTC_TEST_MUX (DR_REG_RTCCNTL_BASE + 0xa8)
|
||
|
|
#define RTC_CNTL_DTEST_RTC 0x00000003
|
||
|
|
#define RTC_CNTL_DTEST_RTC_S 30
|
||
|
|
#define RTC_CNTL_ENT_RTC (BIT(29))
|
||
|
|
#define RTC_CNTL_ENT_RTC_S 29
|
||
|
|
|
||
|
|
#define RTC_SW_CPU_STALL (DR_REG_RTCCNTL_BASE + 0xac)
|
||
|
|
#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F
|
||
|
|
#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26
|
||
|
|
#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F
|
||
|
|
#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20
|
||
|
|
|
||
|
|
#define RTC_STORE4 (DR_REG_RTCCNTL_BASE + 0xb0)
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH4 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH4_S 0
|
||
|
|
|
||
|
|
#define RTC_STORE5 (DR_REG_RTCCNTL_BASE + 0xb4)
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH5 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH5_S 0
|
||
|
|
|
||
|
|
#define RTC_STORE6 (DR_REG_RTCCNTL_BASE + 0xb8)
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH6 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH6_S 0
|
||
|
|
|
||
|
|
#define RTC_STORE7 (DR_REG_RTCCNTL_BASE + 0xbc)
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH7 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_RTC_SCRATCH7_S 0
|
||
|
|
|
||
|
|
#define RTC_DIAG0 (DR_REG_RTCCNTL_BASE + 0xc0)
|
||
|
|
#define RTC_CNTL_RTC_LOW_POWER_DIAG0 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_RTC_LOW_POWER_DIAG0_S 0
|
||
|
|
|
||
|
|
#define RTC_DIAG1 (DR_REG_RTCCNTL_BASE + 0xc4)
|
||
|
|
#define RTC_CNTL_RTC_LOW_POWER_DIAG1 0xFFFFFFFF
|
||
|
|
#define RTC_CNTL_RTC_LOW_POWER_DIAG1_S 0
|
||
|
|
|
||
|
|
#define RTC_HOLD_FORCE (DR_REG_RTCCNTL_BASE + 0xc8)
|
||
|
|
#define RTC_CNTL_X32N_HOLD_FORCE (BIT(17))
|
||
|
|
#define RTC_CNTL_X32N_HOLD_FORCE_S 17
|
||
|
|
#define RTC_CNTL_X32P_HOLD_FORCE (BIT(16))
|
||
|
|
#define RTC_CNTL_X32P_HOLD_FORCE_S 16
|
||
|
|
#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE (BIT(15))
|
||
|
|
#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S 15
|
||
|
|
#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE (BIT(14))
|
||
|
|
#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S 14
|
||
|
|
#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE (BIT(13))
|
||
|
|
#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S 13
|
||
|
|
#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE (BIT(12))
|
||
|
|
#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S 12
|
||
|
|
#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE (BIT(11))
|
||
|
|
#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S 11
|
||
|
|
#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE (BIT(10))
|
||
|
|
#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S 10
|
||
|
|
#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE (BIT(9))
|
||
|
|
#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S 9
|
||
|
|
#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE (BIT(8))
|
||
|
|
#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S 8
|
||
|
|
#define RTC_CNTL_SENSE4_HOLD_FORCE (BIT(7))
|
||
|
|
#define RTC_CNTL_SENSE4_HOLD_FORCE_S 7
|
||
|
|
#define RTC_CNTL_SENSE3_HOLD_FORCE (BIT(6))
|
||
|
|
#define RTC_CNTL_SENSE3_HOLD_FORCE_S 6
|
||
|
|
#define RTC_CNTL_SENSE2_HOLD_FORCE (BIT(5))
|
||
|
|
#define RTC_CNTL_SENSE2_HOLD_FORCE_S 5
|
||
|
|
#define RTC_CNTL_SENSE1_HOLD_FORCE (BIT(4))
|
||
|
|
#define RTC_CNTL_SENSE1_HOLD_FORCE_S 4
|
||
|
|
#define RTC_CNTL_PDAC2_HOLD_FORCE (BIT(3))
|
||
|
|
#define RTC_CNTL_PDAC2_HOLD_FORCE_S 3
|
||
|
|
#define RTC_CNTL_PDAC1_HOLD_FORCE (BIT(2))
|
||
|
|
#define RTC_CNTL_PDAC1_HOLD_FORCE_S 2
|
||
|
|
#define RTC_CNTL_ADC2_HOLD_FORCE (BIT(1))
|
||
|
|
#define RTC_CNTL_ADC2_HOLD_FORCE_S 1
|
||
|
|
#define RTC_CNTL_ADC1_HOLD_FORCE (BIT(0))
|
||
|
|
#define RTC_CNTL_ADC1_HOLD_FORCE_S 0
|
||
|
|
|
||
|
|
#define RTC_EXT_WAKEUP1 (DR_REG_RTCCNTL_BASE + 0xcc)
|
||
|
|
#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18))
|
||
|
|
#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18
|
||
|
|
#define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF
|
||
|
|
#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0
|
||
|
|
|
||
|
|
#define RTC_EXT_WAKEUP1_STATUS (DR_REG_RTCCNTL_BASE + 0xd0)
|
||
|
|
#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF
|
||
|
|
#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0
|
||
|
|
|
||
|
|
#define RTC_BROWN_OUT (DR_REG_RTCCNTL_BASE + 0xd4)
|
||
|
|
#define RTC_CNTL_RTC_BROWN_OUT_DET (BIT(31))
|
||
|
|
#define RTC_CNTL_RTC_BROWN_OUT_DET_S 31
|
||
|
|
#define RTC_CNTL_BROWN_OUT_ENA (BIT(30))
|
||
|
|
#define RTC_CNTL_BROWN_OUT_ENA_S 30
|
||
|
|
#define RTC_CNTL_DBROWN_OUT_THRES 0x00000007
|
||
|
|
#define RTC_CNTL_DBROWN_OUT_THRES_S 27
|
||
|
|
#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26))
|
||
|
|
#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26
|
||
|
|
#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF
|
||
|
|
#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16
|
||
|
|
#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15))
|
||
|
|
#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15
|
||
|
|
#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14))
|
||
|
|
#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14
|
||
|
|
|
||
|
|
#define RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4)
|
||
|
|
#define RTC_MEM_CRC_FINISH (BIT(31))
|
||
|
|
#define RTC_MEM_CRC_FINISH_S (31)
|
||
|
|
#define RTC_MEM_CRC_LEN (0x7ff)
|
||
|
|
#define RTC_MEM_CRC_LEN_S (20)
|
||
|
|
#define RTC_MEM_CRC_ADDR (0x7ff)
|
||
|
|
#define RTC_MEM_CRC_ADDR_S (9)
|
||
|
|
#define RTC_MEM_CRC_START (BIT(8))
|
||
|
|
#define RTC_MEM_CRC_START_S (8)
|
||
|
|
#define RTC_MEM_PID_CONF (0xff)
|
||
|
|
#define RTC_MEM_PID_CONF_S (0)
|
||
|
|
|
||
|
|
#define RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4)
|
||
|
|
|
||
|
|
|
||
|
|
#define RTC_CNTL_DATE (DR_REG_RTCCNTL_BASE + 0x13c)
|
||
|
|
#define RTC_CNTL_RTC_CNTL_DATE 0x0FFFFFFF
|
||
|
|
#define RTC_CNTL_RTC_CNTL_DATE_S 0
|
||
|
|
#define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280
|
||
|
|
|
||
|
|
#endif /* _SOC_RTC_CNTL_REG_H_ */
|