Crash_Override/MMDVMHost-Private
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

Add Windows support for the DMR Access Control.

Browse source
This commit is contained in:
Jonathan Naylor 2016-07-11 17:41:53 +01:00
parent 154d2a7bf9
commit 58061be4c9
4 changed files with 56 additions and 70 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

98
DMRAccessControl.cpp
View file

@ -32,16 +32,17 @@ std::vector<unsigned int> DMRAccessControl::m_dstWhiteListSlot2NET;
std::vector<unsigned int> DMRAccessControl::m_SrcIdBlacklist; std::vector<unsigned int> DMRAccessControl::m_SrcIdBlacklist;
std::vector<unsigned int> DMRAccessControl::m_prefixes; std::vector<unsigned int> DMRAccessControl::m_prefixes;
bool DMRAccessControl::m_selfOnly;
unsigned int DMRAccessControl::m_id; bool DMRAccessControl::m_selfOnly = false;
unsigned int DMRAccessControl::m_id = 0U;
void DMRAccessControl::init(const std::vector<unsigned int>& DstIdBlacklistSlot1RF, const std::vector<unsigned int>& DstIdWhitelistSlot1RF, const std::vector<unsigned int>& DstIdBlacklistSlot2RF, const std::vector<unsigned int>& DstIdWhitelistSlot2RF, const std::vector<unsigned int>& DstIdBlacklistSlot1NET, const std::vector<unsigned int>& DstIdWhitelistSlot1NET, const std::vector<unsigned int>& DstIdBlacklistSlot2NET, const std::vector<unsigned int>& DstIdWhitelistSlot2NET, const std::vector<unsigned int>& SrcIdBlacklist, bool selfOnly, const std::vector<unsigned int>& prefixes,unsigned int id) void DMRAccessControl::init(const std::vector<unsigned int>& DstIdBlacklistSlot1RF, const std::vector<unsigned int>& DstIdWhitelistSlot1RF, const std::vector<unsigned int>& DstIdBlacklistSlot2RF, const std::vector<unsigned int>& DstIdWhitelistSlot2RF, const std::vector<unsigned int>& DstIdBlacklistSlot1NET, const std::vector<unsigned int>& DstIdWhitelistSlot1NET, const std::vector<unsigned int>& DstIdBlacklistSlot2NET, const std::vector<unsigned int>& DstIdWhitelistSlot2NET, const std::vector<unsigned int>& SrcIdBlacklist, bool selfOnly, const std::vector<unsigned int>& prefixes,unsigned int id)
{ {
m_dstBlackListSlot1RF = DstIdBlacklistSlot1RF;
m_dstBlackListSlot1RF = DstIdBlacklistSlot1RF; m_dstWhiteListSlot1RF = DstIdWhitelistSlot1RF;
m_dstWhiteListSlot1RF = DstIdWhitelistSlot1RF; m_dstBlackListSlot2RF = DstIdBlacklistSlot2RF;
m_dstBlackListSlot2RF = DstIdBlacklistSlot2RF; m_dstWhiteListSlot2RF = DstIdWhitelistSlot2RF;
m_dstWhiteListSlot2RF = DstIdWhitelistSlot2RF;
m_dstBlackListSlot1NET = DstIdBlacklistSlot1NET; m_dstBlackListSlot1NET = DstIdBlacklistSlot1NET;
m_dstWhiteListSlot1NET = DstIdWhitelistSlot1NET; m_dstWhiteListSlot1NET = DstIdWhitelistSlot1NET;
m_dstBlackListSlot2NET = DstIdBlacklistSlot2NET; m_dstBlackListSlot2NET = DstIdBlacklistSlot2NET;
@ -50,40 +51,32 @@ void DMRAccessControl::init(const std::vector<unsigned int>& DstIdBlacklistSlot1
bool DMRAccessControl::DstIdBlacklist(unsigned int did, unsigned int slot, bool network) bool DMRAccessControl::DstIdBlacklist(unsigned int did, unsigned int slot, bool network)
{ {
static std::vector<unsigned int> Blacklist; static std::vector<unsigned int> blacklist;
if (slot == 1U) { if (slot == 1U) {
if (network)
if (network) { blacklist = m_dstBlackListSlot1NET;
Blacklist = m_dstBlackListSlot1NET; else
} blacklist = m_dstBlackListSlot1RF;
else {
Blacklist = m_dstBlackListSlot1RF;
}
} else { } else {
if (network) { if (network)
Blacklist = m_dstBlackListSlot2NET; blacklist = m_dstBlackListSlot2NET;
} else
else { blacklist = m_dstBlackListSlot2RF;
Blacklist = m_dstBlackListSlot2RF;
}
} }
if (std::find(Blacklist.begin(), Blacklist.end(), did) != Blacklist.end())
return true;
return false; return std::find(blacklist.begin(), blacklist.end(), did) != blacklist.end();
} }
bool DMRAccessControl::DstIdWhitelist(unsigned int did, unsigned int slot, bool gt4k, bool network) bool DMRAccessControl::DstIdWhitelist(unsigned int did, unsigned int slot, bool gt4k, bool network)
{ {
if (network) { if (network) {
if (slot == 1U) { if (slot == 1U) {
if (m_dstWhiteListSlot1NET.size() == 0U) if (m_dstWhiteListSlot1NET.size() == 0U)
return true; return true;
// No reflectors on slot1, so we only allow all IDs over 99999 unless specifically whitelisted. // No reflectors on slot1, so we only allow all IDs over 99999 unless specifically whitelisted.
//Allow traffic to TG0 as I think this is a special case - need to confirm // Allow traffic to TG0 as I think this is a special case - need to confirm
if (gt4k) { if (gt4k) {
if (std::find(m_dstWhiteListSlot1NET.begin(), m_dstWhiteListSlot1NET.end(), did) != m_dstWhiteListSlot1NET.end() || did >= 99999U || did == 0) if (std::find(m_dstWhiteListSlot1NET.begin(), m_dstWhiteListSlot1NET.end(), did) != m_dstWhiteListSlot1NET.end() || did >= 99999U || did == 0)
return true; return true;
@ -95,34 +88,31 @@ bool DMRAccessControl::DstIdWhitelist(unsigned int did, unsigned int slot, bool
if (m_dstWhiteListSlot2NET.size() == 0U) if (m_dstWhiteListSlot2NET.size() == 0U)
return true; return true;
//On slot2 we allow reflector control IDs, but not secondary TG IDs unless specifically listed. Also allow echo. // On slot2 we allow reflector control IDs, but not secondary TG IDs unless specifically listed. Also allow echo.
if (gt4k) { if (gt4k) {
if (std::find(m_dstWhiteListSlot2NET.begin(), m_dstWhiteListSlot2NET.end(), did) != m_dstWhiteListSlot2NET.end() || did == 0) if (std::find(m_dstWhiteListSlot2NET.begin(), m_dstWhiteListSlot2NET.end(), did) != m_dstWhiteListSlot2NET.end() || did == 0)
return true; return true;
// If dstId in secondary TG range or whitelist
//if dstId in secondary TG range or whitelist
else if (did >= 4000) { else if (did >= 4000) {
if (did > 5000U && did < 10000U) if (did > 5000U && did < 10000U)
return false; return false;
else else
return true; return true;
} }
} else { } else {
if (std::find(m_dstWhiteListSlot2NET.begin(), m_dstWhiteListSlot2NET.end(), did) != m_dstWhiteListSlot2NET.end()) if (std::find(m_dstWhiteListSlot2NET.begin(), m_dstWhiteListSlot2NET.end(), did) != m_dstWhiteListSlot2NET.end())
return true; return true;
} }
} }
return false; return false;
} else { } else {
if (slot == 1U) { if (slot == 1U) {
if (m_dstWhiteListSlot1RF.size() == 0U) if (m_dstWhiteListSlot1RF.size() == 0U)
return true; return true;
// No reflectors on slot1, so we only allow all IDs over 99999 unless specifically whitelisted. // No reflectors on slot1, so we only allow all IDs over 99999 unless specifically whitelisted.
//Allow traffic to TG0 as I think this is a special case - need to confirm // Allow traffic to TG0 as I think this is a special case - need to confirm
if (gt4k) { if (gt4k) {
if (std::find(m_dstWhiteListSlot1RF.begin(), m_dstWhiteListSlot1RF.end(), did) != m_dstWhiteListSlot1RF.end() || did >= 99999U || did == 0) if (std::find(m_dstWhiteListSlot1RF.begin(), m_dstWhiteListSlot1RF.end(), did) != m_dstWhiteListSlot1RF.end() || did >= 99999U || did == 0)
return true; return true;
@ -134,26 +124,24 @@ bool DMRAccessControl::DstIdWhitelist(unsigned int did, unsigned int slot, bool
if (m_dstWhiteListSlot2RF.size() == 0U) if (m_dstWhiteListSlot2RF.size() == 0U)
return true; return true;
//On slot2 we allow reflector control IDs, but not secondary TG IDs unless specifically listed. Also allow echo. // On slot2 we allow reflector control IDs, but not secondary TG IDs unless specifically listed. Also allow echo.
if (gt4k) { if (gt4k) {
if (std::find(m_dstWhiteListSlot2RF.begin(), m_dstWhiteListSlot2RF.end(), did) != m_dstWhiteListSlot2RF.end() || did == 0) if (std::find(m_dstWhiteListSlot2RF.begin(), m_dstWhiteListSlot2RF.end(), did) != m_dstWhiteListSlot2RF.end() || did == 0)
return true; return true;
// If dstId in secondary TG range or whitelist
//if dstId in secondary TG range or whitelist
else if (did >= 4000) { else if (did >= 4000) {
if (did > 5000U && did < 10000U) if (did > 5000U && did < 10000U)
return false; return false;
else else
return true; return true;
} }
} else { } else {
if (std::find(m_dstWhiteListSlot2RF.begin(), m_dstWhiteListSlot2RF.end(), did) != m_dstWhiteListSlot2RF.end()) if (std::find(m_dstWhiteListSlot2RF.begin(), m_dstWhiteListSlot2RF.end(), did) != m_dstWhiteListSlot2RF.end())
return true; return true;
} }
} }
return false; return false;
} }
} }
@ -180,19 +168,15 @@ bool DMRAccessControl::validateAccess (unsigned int src_id, unsigned int dst_id,
{ {
// source ID validation is only applied to RF traffic // source ID validation is only applied to RF traffic
if (!network && !DMRAccessControl::validateSrcId(src_id)) { if (!network && !DMRAccessControl::validateSrcId(src_id)) {
LogMessage("DMR Slot %u, invalid access attempt from %u (blacklisted)", slot, src_id); LogMessage("DMR Slot %u, invalid access attempt from %u (blacklisted)", slot, src_id);
return false; return false;
} else if (DMRAccessControl::DstIdBlacklist(dst_id, slot, network)) {
} LogMessage("DMR Slot %u, invalid access attempt to TG%u (TG blacklisted)", slot, dst_id);
else if (DMRAccessControl::DstIdBlacklist(dst_id, slot, network)) { return false;
LogMessage("DMR Slot %u, invalid access attempt to TG%u (TG blacklisted)", slot, dst_id); } else if (!DMRAccessControl::DstIdWhitelist(dst_id, slot, true, network)) {
return false; LogMessage("DMR Slot %u, invalid access attempt to TG%u (TG not in whitelist)", slot, dst_id);
} return false;
else if (!DMRAccessControl::DstIdWhitelist(dst_id, slot, true, network)) { } else {
LogMessage("DMR Slot %u, invalid access attempt to TG%u (TG not in whitelist)", slot, dst_id); return true;
return false; }
}
else
return true;
} }

20
DMRAccessControl.h
View file

@ -19,13 +19,10 @@
class DMRAccessControl { class DMRAccessControl {
public: public:
static bool validateAccess (unsigned int src_id, unsigned int dst_id, unsigned int slot, bool network); static bool validateAccess (unsigned int src_id, unsigned int dst_id, unsigned int slot, bool network);
static void init(const std::vector<unsigned int>& DstIdBlacklistSlot1RF, const std::vector<unsigned int>& DstIdWhitelistSlot1RF, const std::vector<unsigned int>& DstIdBlacklistSlot2RF, const std::vector<unsigned int>& DstIdWhitelistSlot2RF, const std::vector<unsigned int>& DstIdBlacklistSlot1NET, const std::vector<unsigned int>& DstIdWhitelistSlot1NET, const std::vector<unsigned int>& DstIdBlacklistSlot2NET, const std::vector<unsigned int>& DstIdWhitelistSlot2NET, const std::vector<unsigned int>& SrcIdBlacklist, bool selfOnly, const std::vector<unsigned int>& prefixes,unsigned int id);
static void init(const std::vector<unsigned int>& DstIdBlacklistSlot1RF, const std::vector<unsigned int>& DstIdWhitelistSlot1RF, const std::vector<unsigned int>& DstIdBlacklistSlot2RF, const std::vector<unsigned int>& DstIdWhitelistSlot2RF, const std::vector<unsigned int>& DstIdBlacklistSlot1NET, const std::vector<unsigned int>& DstIdWhitelistSlot1NET, const std::vector<unsigned int>& DstIdBlacklistSlot2NET, const std::vector<unsigned int>& DstIdWhitelistSlot2NET, const std::vector<unsigned int>& SrcIdBlacklist, bool selfOnly, const std::vector<unsigned int>& prefixes,unsigned int id);
private: private:
static std::vector<unsigned int> m_dstBlackListSlot1RF; static std::vector<unsigned int> m_dstBlackListSlot1RF;
static std::vector<unsigned int> m_dstBlackListSlot2RF; static std::vector<unsigned int> m_dstBlackListSlot2RF;
@ -36,21 +33,18 @@ private:
static std::vector<unsigned int> m_dstBlackListSlot2NET; static std::vector<unsigned int> m_dstBlackListSlot2NET;
static std::vector<unsigned int> m_dstWhiteListSlot1NET; static std::vector<unsigned int> m_dstWhiteListSlot1NET;
static std::vector<unsigned int> m_dstWhiteListSlot2NET; static std::vector<unsigned int> m_dstWhiteListSlot2NET;
static std::vector<unsigned int> m_SrcIdBlacklist; static std::vector<unsigned int> m_SrcIdBlacklist;
static std::vector<unsigned int> m_prefixes; static std::vector<unsigned int> m_prefixes;
static bool m_selfOnly; static bool m_selfOnly;
static unsigned int m_id; static unsigned int m_id;
static bool DstIdBlacklist(unsigned int did,unsigned int slot, bool network); static bool DstIdBlacklist(unsigned int did,unsigned int slot, bool network);
static bool DstIdWhitelist(unsigned int did,unsigned int slot,bool gt4k, bool network); static bool DstIdWhitelist(unsigned int did,unsigned int slot,bool gt4k, bool network);
static bool validateSrcId(unsigned int id); static bool validateSrcId(unsigned int id);
}; };
#endif #endif

2
MMDVMHost.vcxproj
View file

@ -152,6 +152,7 @@
<ClInclude Include="CRC.h" /> <ClInclude Include="CRC.h" />
<ClInclude Include="Defines.h" /> <ClInclude Include="Defines.h" />
<ClInclude Include="Display.h" /> <ClInclude Include="Display.h" />
<ClInclude Include="DMRAccessControl.h" />
<ClInclude Include="DMRControl.h" /> <ClInclude Include="DMRControl.h" />
<ClInclude Include="DMRCSBK.h" /> <ClInclude Include="DMRCSBK.h" />
<ClInclude Include="DMRData.h" /> <ClInclude Include="DMRData.h" />
@ -206,6 +207,7 @@
<ClCompile Include="Conf.cpp" /> <ClCompile Include="Conf.cpp" />
<ClCompile Include="CRC.cpp" /> <ClCompile Include="CRC.cpp" />
<ClCompile Include="Display.cpp" /> <ClCompile Include="Display.cpp" />
<ClCompile Include="DMRAccessControl.cpp" />
<ClCompile Include="DMRControl.cpp" /> <ClCompile Include="DMRControl.cpp" />
<ClCompile Include="DMRCSBK.cpp" /> <ClCompile Include="DMRCSBK.cpp" />
<ClCompile Include="DMRData.cpp" /> <ClCompile Include="DMRData.cpp" />

6
MMDVMHost.vcxproj.filters
View file

@ -170,6 +170,9 @@
<ClInclude Include="DMRTrellis.h"> <ClInclude Include="DMRTrellis.h">
<Filter>Header Files</Filter> <Filter>Header Files</Filter>
</ClInclude> </ClInclude>
<ClInclude Include="DMRAccessControl.h">
<Filter>Header Files</Filter>
</ClInclude>
</ItemGroup> </ItemGroup>
<ItemGroup> <ItemGroup>
<ClCompile Include="BPTC19696.cpp"> <ClCompile Include="BPTC19696.cpp">
@ -313,5 +316,8 @@
<ClCompile Include="DMRTrellis.cpp"> <ClCompile Include="DMRTrellis.cpp">
<Filter>Source Files</Filter> <Filter>Source Files</Filter>
</ClCompile> </ClCompile>
<ClCompile Include="DMRAccessControl.cpp">
<Filter>Source Files</Filter>
</ClCompile>
</ItemGroup> </ItemGroup>
</Project> </Project>