2016-07-10 10:47:23 +00:00
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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*/
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#include "DMRAccessControl.h"
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2016-07-10 16:32:00 +00:00
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#include "Log.h"
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2016-07-10 10:47:23 +00:00
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#include <algorithm>
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#include <vector>
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2016-07-10 20:37:11 +00:00
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std::vector<unsigned int> DMRAccessControl::m_dstBlackListSlot1RF;
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std::vector<unsigned int> DMRAccessControl::m_dstBlackListSlot2RF;
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std::vector<unsigned int> DMRAccessControl::m_dstWhiteListSlot1RF;
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std::vector<unsigned int> DMRAccessControl::m_dstWhiteListSlot2RF;
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std::vector<unsigned int> DMRAccessControl::m_dstBlackListSlot1NET;
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std::vector<unsigned int> DMRAccessControl::m_dstBlackListSlot2NET;
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std::vector<unsigned int> DMRAccessControl::m_dstWhiteListSlot1NET;
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std::vector<unsigned int> DMRAccessControl::m_dstWhiteListSlot2NET;
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2016-07-10 10:47:23 +00:00
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2016-07-10 15:46:02 +00:00
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std::vector<unsigned int> DMRAccessControl::m_SrcIdBlacklist;
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std::vector<unsigned int> DMRAccessControl::m_prefixes;
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2016-07-11 16:41:53 +00:00
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bool DMRAccessControl::m_selfOnly = false;
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unsigned int DMRAccessControl::m_id = 0U;
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2016-07-10 15:46:02 +00:00
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2016-07-10 20:37:11 +00:00
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void DMRAccessControl::init(const std::vector<unsigned int>& DstIdBlacklistSlot1RF, const std::vector<unsigned int>& DstIdWhitelistSlot1RF, const std::vector<unsigned int>& DstIdBlacklistSlot2RF, const std::vector<unsigned int>& DstIdWhitelistSlot2RF, const std::vector<unsigned int>& DstIdBlacklistSlot1NET, const std::vector<unsigned int>& DstIdWhitelistSlot1NET, const std::vector<unsigned int>& DstIdBlacklistSlot2NET, const std::vector<unsigned int>& DstIdWhitelistSlot2NET, const std::vector<unsigned int>& SrcIdBlacklist, bool selfOnly, const std::vector<unsigned int>& prefixes,unsigned int id)
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{
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m_dstBlackListSlot1RF = DstIdBlacklistSlot1RF;
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m_dstWhiteListSlot1RF = DstIdWhitelistSlot1RF;
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m_dstBlackListSlot2RF = DstIdBlacklistSlot2RF;
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m_dstWhiteListSlot2RF = DstIdWhitelistSlot2RF;
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2016-07-10 20:37:11 +00:00
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m_dstBlackListSlot1NET = DstIdBlacklistSlot1NET;
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m_dstWhiteListSlot1NET = DstIdWhitelistSlot1NET;
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m_dstBlackListSlot2NET = DstIdBlacklistSlot2NET;
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m_dstWhiteListSlot2NET = DstIdWhitelistSlot2NET;
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2016-07-10 10:47:23 +00:00
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}
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2016-07-10 20:37:11 +00:00
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bool DMRAccessControl::DstIdBlacklist(unsigned int did, unsigned int slot, bool network)
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{
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2016-07-11 16:41:53 +00:00
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static std::vector<unsigned int> blacklist;
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2016-07-10 20:37:11 +00:00
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2016-07-10 10:47:23 +00:00
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if (slot == 1U) {
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2016-07-11 16:41:53 +00:00
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if (network)
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blacklist = m_dstBlackListSlot1NET;
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else
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blacklist = m_dstBlackListSlot1RF;
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2016-07-10 10:47:23 +00:00
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} else {
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2016-07-11 16:41:53 +00:00
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if (network)
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blacklist = m_dstBlackListSlot2NET;
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else
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blacklist = m_dstBlackListSlot2RF;
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2016-07-10 10:47:23 +00:00
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}
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2016-07-11 16:41:53 +00:00
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return std::find(blacklist.begin(), blacklist.end(), did) != blacklist.end();
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2016-07-10 10:47:23 +00:00
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}
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2016-07-10 20:37:11 +00:00
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bool DMRAccessControl::DstIdWhitelist(unsigned int did, unsigned int slot, bool gt4k, bool network)
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{
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2016-07-10 20:37:11 +00:00
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if (network) {
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if (slot == 1U) {
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if (m_dstWhiteListSlot1NET.size() == 0U)
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return true;
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2016-07-10 10:47:23 +00:00
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2016-07-10 20:37:11 +00:00
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// No reflectors on slot1, so we only allow all IDs over 99999 unless specifically whitelisted.
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2016-07-11 16:41:53 +00:00
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// Allow traffic to TG0 as I think this is a special case - need to confirm
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2016-07-10 20:37:11 +00:00
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if (gt4k) {
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if (std::find(m_dstWhiteListSlot1NET.begin(), m_dstWhiteListSlot1NET.end(), did) != m_dstWhiteListSlot1NET.end() || did >= 99999U || did == 0)
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return true;
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} else {
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if (std::find(m_dstWhiteListSlot1NET.begin(), m_dstWhiteListSlot1NET.end(), did) != m_dstWhiteListSlot1NET.end() || did == 0)
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return true;
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}
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} else {
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if (m_dstWhiteListSlot2NET.size() == 0U)
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return true;
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2016-07-11 16:41:53 +00:00
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// On slot2 we allow reflector control IDs, but not secondary TG IDs unless specifically listed. Also allow echo.
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2016-07-10 20:37:11 +00:00
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if (gt4k) {
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if (std::find(m_dstWhiteListSlot2NET.begin(), m_dstWhiteListSlot2NET.end(), did) != m_dstWhiteListSlot2NET.end() || did == 0)
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2016-07-11 16:41:53 +00:00
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return true;
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// If dstId in secondary TG range or whitelist
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2016-07-10 20:37:11 +00:00
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else if (did >= 4000) {
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if (did > 5000U && did < 10000U)
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return false;
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else
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return true;
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}
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2016-07-11 16:41:53 +00:00
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} else {
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2016-07-10 20:37:11 +00:00
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if (std::find(m_dstWhiteListSlot2NET.begin(), m_dstWhiteListSlot2NET.end(), did) != m_dstWhiteListSlot2NET.end())
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return true;
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}
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}
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return false;
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2016-07-10 10:47:23 +00:00
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} else {
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2016-07-10 20:37:11 +00:00
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if (slot == 1U) {
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if (m_dstWhiteListSlot1RF.size() == 0U)
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return true;
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2016-07-10 10:47:23 +00:00
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2016-07-10 20:37:11 +00:00
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// No reflectors on slot1, so we only allow all IDs over 99999 unless specifically whitelisted.
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2016-07-11 16:41:53 +00:00
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// Allow traffic to TG0 as I think this is a special case - need to confirm
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2016-07-10 20:37:11 +00:00
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if (gt4k) {
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if (std::find(m_dstWhiteListSlot1RF.begin(), m_dstWhiteListSlot1RF.end(), did) != m_dstWhiteListSlot1RF.end() || did >= 99999U || did == 0)
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return true;
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} else {
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if (std::find(m_dstWhiteListSlot1RF.begin(), m_dstWhiteListSlot1RF.end(), did) != m_dstWhiteListSlot1RF.end() || did == 0)
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return true;
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}
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} else {
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if (m_dstWhiteListSlot2RF.size() == 0U)
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2016-07-10 10:47:23 +00:00
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return true;
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2016-07-10 20:37:11 +00:00
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2016-07-11 16:41:53 +00:00
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// On slot2 we allow reflector control IDs, but not secondary TG IDs unless specifically listed. Also allow echo.
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2016-07-10 20:37:11 +00:00
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if (gt4k) {
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2016-07-11 16:41:53 +00:00
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if (std::find(m_dstWhiteListSlot2RF.begin(), m_dstWhiteListSlot2RF.end(), did) != m_dstWhiteListSlot2RF.end() || did == 0)
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return true;
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// If dstId in secondary TG range or whitelist
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2016-07-10 20:37:11 +00:00
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else if (did >= 4000) {
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if (did > 5000U && did < 10000U)
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return false;
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else
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return true;
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}
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2016-07-11 16:41:53 +00:00
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} else {
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2016-07-10 20:37:11 +00:00
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if (std::find(m_dstWhiteListSlot2RF.begin(), m_dstWhiteListSlot2RF.end(), did) != m_dstWhiteListSlot2RF.end())
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return true;
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}
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}
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2016-07-11 16:41:53 +00:00
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return false;
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2016-07-10 10:47:23 +00:00
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}
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}
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2016-07-10 15:46:02 +00:00
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bool DMRAccessControl::validateSrcId(unsigned int id)
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{
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if (m_selfOnly) {
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return id == m_id;
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} else {
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if (std::find(m_SrcIdBlacklist.begin(), m_SrcIdBlacklist.end(), id) != m_SrcIdBlacklist.end())
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return false;
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unsigned int prefix = id / 10000U;
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if (prefix == 0U || prefix > 999U)
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return false;
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if (m_prefixes.size() == 0U)
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return true;
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return std::find(m_prefixes.begin(), m_prefixes.end(), prefix) != m_prefixes.end();
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}
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}
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2016-07-10 16:32:00 +00:00
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2016-07-10 16:48:09 +00:00
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bool DMRAccessControl::validateAccess (unsigned int src_id, unsigned int dst_id, unsigned int slot, bool network)
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2016-07-10 16:32:00 +00:00
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{
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2016-07-10 16:48:09 +00:00
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// source ID validation is only applied to RF traffic
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if (!network && !DMRAccessControl::validateSrcId(src_id)) {
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2016-07-11 16:41:53 +00:00
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LogMessage("DMR Slot %u, invalid access attempt from %u (blacklisted)", slot, src_id);
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return false;
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} else if (DMRAccessControl::DstIdBlacklist(dst_id, slot, network)) {
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LogMessage("DMR Slot %u, invalid access attempt to TG%u (TG blacklisted)", slot, dst_id);
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return false;
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} else if (!DMRAccessControl::DstIdWhitelist(dst_id, slot, true, network)) {
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LogMessage("DMR Slot %u, invalid access attempt to TG%u (TG not in whitelist)", slot, dst_id);
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return false;
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} else {
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return true;
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}
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2016-07-10 16:32:00 +00:00
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}
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