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4778 commits 13 branches 131 tags 69 MiB
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Author SHA1 Message Date
DJ2LS
9a263757b1
first working data channel 2021-02-28 15:24:14 +01:00
DJ2LS
c9c869e802
n_tx_preamble_modem_samples function 
n_tx_preamble_modem_samples = self.c_lib.freedv_get_n_tx_preamble_modem_samples(freedv)
 2021-02-25 08:40:48 +01:00
DJ2LS
76aa3094fc
fixed data type for ARQ_STATE 2021-02-24 17:41:14 +01:00
DJ2LS
697106b567
beacon placeholder and connect optimization 2021-02-24 17:29:08 +01:00
DJ2LS
812e00a403
first connect, cq and ping handler 2021-02-24 16:47:52 +01:00
DJ2LS
55d56b8e83
renamed arq module to data_handler 2021-02-24 14:22:28 +01:00
DJ2LS
adfb9d3625
switching to signalling mode as default 
necessary for mode gear shifting, ping, cq ...
 2021-02-24 14:16:29 +01:00
DJ2LS
c83ebf742b
Merge pull request #27 from DJ2LS/Doc 
Initial Documentation files
 2021-02-24 09:15:50 +01:00
DJ2LS
b1e31b729a
Delete test 2021-02-24 09:14:57 +01:00
DJ2LS
d6a6a655ff
Delete FreeDV-JATE Frametypes.xlsx - Overview.pdf 2021-02-24 09:14:46 +01:00
DJ2LS
fdaccfdb68
Delete FreeDV-JATE Frametypes.xlsx - ARQ.pdf 2021-02-24 09:14:39 +01:00
DJ2LS
10b2574442
Add files via upload 2021-02-24 09:14:28 +01:00
DJ2LS
c7e62348e0
Create test 2021-02-24 09:14:07 +01:00
DJ2LS
c7379af865
Add files via upload 2021-02-24 09:12:32 +01:00
DJ2LS
327f07ed4d
modem optimization 2021-02-23 13:21:41 +01:00
DJ2LS
2c7ca05bee
maybe fix of "stuck in sync" 
fixed a lot of buffer allocation problems
 2021-02-23 11:31:19 +01:00
DJ2LS
681fe6d8ac
first hamlib integration 
still only for development purposes.
 2021-02-19 11:08:44 +01:00
DJ2LS
7f1a502a81
PTT_STATE 2021-02-19 09:58:12 +01:00
DJ2LS
60bea070ec
TNC_STATE machine 2021-02-19 09:50:04 +01:00
DJ2LS
8a713eb272
Merge branch 'main' into dev 2021-02-18 16:54:21 +01:00
DJ2LS
f118a3878a
Merge pull request #25 from DJ2LS/SOCKETv1 
new socket handler
 2021-02-18 16:37:54 +01:00
DJ2LS
f310a1b925
Update README.md 2021-02-18 16:26:51 +01:00
DJ2LS
4bd8119b25
Update README.md 2021-02-18 15:27:55 +01:00
DJ2LS
1f1234254a
add del rx_buffer via sock 2021-02-18 15:11:37 +01:00
DJ2LS
171dc0e5a0
single threading instead of multithreading per req 2021-02-18 11:14:47 +01:00
DJ2LS
a36b85aca3
updated callsin and buffer readings 2021-02-16 22:41:06 +01:00
DJ2LS
533d797be3
new commands 2021-02-16 20:49:02 +01:00
DJ2LS
2b708f8453
new socket handler 2021-02-16 19:39:08 +01:00
DJ2LS
093fa3acfc
Update README.md 2021-02-16 17:10:24 +01:00
DJ2LS
4805ad318e
Update README.md 2021-02-16 17:08:41 +01:00
DJ2LS
bd659f168f
Update README.md 2021-02-16 16:55:25 +01:00
DJ2LS
f789925b50
Merge pull request #24 from DJ2LS/ARQv2 
ARQv2
 2021-02-16 16:49:06 +01:00
DJ2LS
829692a13d
cleanup 2021-02-16 14:36:26 +01:00
DJ2LS
4e3d2cc158
cleanup & optimized data/cmd socket 2021-02-16 14:36:01 +01:00
DJ2LS
a5d0e6e608
switch to sock file 2021-02-16 14:24:36 +01:00
DJ2LS
1969349b50
code cleanup 2021-02-16 14:23:57 +01:00
DJ2LS
129e0c0645
improved single frame transmission 
solved timing issues
 2021-02-15 16:33:43 +01:00
DJ2LS
81cbb427e7
erase frame buffer if first frame 
prevent a buffer issue if a transmission is stuck and we receive a new data frame
 2021-02-10 21:30:46 +01:00
DJ2LS
63628f56d3
improved logging 
now with colors and timestamps...
 2021-02-10 19:43:59 +01:00
DJ2LS
75027330d0
Delete static.py 2021-02-10 15:05:47 +01:00
DJ2LS
6ad66452c7
Delete modem.py 2021-02-10 15:05:41 +01:00
DJ2LS
d81d1e49e5
Delete arq.py 2021-02-10 15:05:35 +01:00
DJ2LS
c709f8b604
improved states 2021-02-10 15:05:21 +01:00
DJ2LS
be7bc9744f
improved states 2021-02-10 15:05:03 +01:00
DJ2LS
cebaf469db
improved helpers 2021-02-10 15:04:18 +01:00
DJ2LS
91114d0db2
improved state and timing 2021-02-09 14:27:36 +01:00
DJ2LS
0a8ea24112
improved RPT 
Now working, but still timing issues and stuck in sync
 2021-02-09 12:35:24 +01:00
DJ2LS
6adf7db483
bleeding edge ARQ RPT 
no working, but with tooo much debugging output
furthermore the frame ACK is not working correctly on the TX side
 2021-02-08 21:25:22 +01:00
DJ2LS
eb7f98e2e1
RPT FRAME 
first bleeding edge attempt
not completed yet
 2021-02-08 19:00:12 +01:00
DJ2LS
06cb35276e
removed burst crc 
the burst CRC is not needed, because we only receive frames with correct CRC. So its more important to create a correct ARQ algorithm. The 2byte CRC has been removed bei 2 x CRC8 for DX call sign and own callsign
 2021-02-08 16:33:11 +01:00