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modem optimization

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DJ2LS 2021-02-23 13:21:41 +01:00 committed by GitHub
parent 2c7ca05bee
commit 327f07ed4d
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GPG key ID: 4AEE18F83AFDEB23
1 changed files with 3 additions and 17 deletions
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16
modem.py
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@ -137,6 +137,7 @@ class RF():
self.my_rig.set_ptt(self.hamlib_ptt_type,0)
static.PTT_STATE = False
static.ARQ_STATE = 'RECEIVING_DATA'
#--------------------------------------------------------------------------------------------------------
# GET ARQ BURST FRAME VOM BUFFER AND MODULATE IT
@ -281,13 +282,6 @@ class RF():
stuck_in_sync_10_counter = 0
#
#for i in range(0,3):
# data_dummy = bytes(self.c_lib.freedv_nin(freedv_data))
# signalling_dummy = bytes(self.c_lib.freedv_nin(freedv_signalling))
# self.c_lib.freedv_rawdatarx(freedv_data, data_bytes_out, data_dummy)
# self.c_lib.freedv_rawdatarx(freedv_signalling, data_bytes_out, signalling_dummy)
while static.ARQ_STATE == 'RECEIVING_DATA':
time.sleep(0.01)
@ -358,14 +352,6 @@ class RF():
logging.debug("LAST FRAME ---> UNSYNC")
self.c_lib.freedv_set_sync(freedv_data, 0) #FORCE UNSYNC
# clear demod buffer
#for i in range(0,3):
# data_dummy = bytes(self.c_lib.freedv_nin(freedv_data))
# signalling_dummy = bytes(self.c_lib.freedv_nin(freedv_signalling))
# self.c_lib.freedv_rawdatarx(freedv_data, data_bytes_out, data_dummy)
# self.c_lib.freedv_rawdatarx(freedv_signalling, data_bytes_out, signalling_dummy)
#while static.ARQ_STATE == 'IDLE' or static.ARQ_STATE == 'RECEIVING_SIGNALLING':
while static.ARQ_STATE == 'RECEIVING_SIGNALLING':